Výsledky vyhledávání - "Craig, Huffman"

Selectivity in Thermal Atomic Layer Etching Using Sequential, Self-Limiting Fluorination and Ligand-Exchange Reactions

Autor: Craig Huffman, Steven M. George, Younghee Lee

Publikováno v: Chemistry of Materials. 28:7657-7665

Atomic layer etching (ALE) can result from sequential, self-limiting thermal reactions. The reactions during thermal ALE are defined by fluorination followed by ligand exchange using metal precursors. The metal precursors introduce various ligands th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::67f6801f6dad3366eba9122e2d29b629
https://doi.org/10.1021/acs.chemmater.6b02543

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Controlled Layer-by-Layer Etching of MoS2

Autor: Lin Taizhe, Min-Hwan Jeon, Sehan Lee, Craig Huffman, Jin Yong Lee, Kyong-nam Kim, Baotao Kang, Wei Han, JeaHoo Jeon, Sungjoo Lee, Geun Young Yeom

Publikováno v: ACS Applied Materials & Interfaces. 7:15892-15897

Two-dimensional (2D) metal dichalcogenides like molybdenum disulfide (MoS2) may provide a pathway to high-mobility channel materials that are needed for beyond-complementary metal-oxide-semiconductor (CMOS) devices. Controlling the thickness of these

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https://doi.org/10.1021/acsami.5b03491

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Variation in process conditions of porogen-based low-k films: A method to improve performance without changing existing process steps in a sub-100nm Cu damascene integration route

Autor: H. Sprey, D. De Roest, J. Labat, Nobuyoshi Kobayashi, Craig Huffman, Patrick Verdonck, Kiyohiro Matsushita, J. Beynet, Gerald Beyer, Shinya Kaneko, Youssef Travaly

Publikováno v: Microelectronic Engineering. 87:311-315

This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varyin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bcf2ebbc95d33e57d77f1874d0d27319
https://doi.org/10.1016/j.mee.2009.06.036

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Controlled Layer-by-Layer Etching of MoS₂

Autor: TaiZhe, Lin, BaoTao, Kang, MinHwan, Jeon, Craig, Huffman, JeaHoo, Jeon, SungJoo, Lee, Wei, Han, JinYong, Lee, SeHan, Lee, GeunYoung, Yeom, KyongNam, Kim

Publikováno v: ACS applied materialsinterfaces. 7(29)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=pmid________::521a7098e166733c75ec089347af220b
https://pubmed.ncbi.nlm.nih.gov/26091282

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Moving from thin films to atomic layers — Atomic layer etching

Autor: Eric A. Joseph, Craig Huffman, Satyavolu PapaRao

Publikováno v: 2015 International Symposium on VLSI Technology, Systems and Applications.

Controlled layer by layer material removal will be required for device fabrication in the future. Atomic level etch is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reacti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f4b4b1e91a5fc39bf310dadd113a2ff5
https://doi.org/10.1109/vlsi-tsa.2015.7117594

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Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Autor: Naim Moumen, Seung-Chul Song, Zhibo Zhang, Paul Kirsch, Prashant Majhi, Rino Choi, Byoung Hun Lee, Craig Huffman, S.H. Bae, J.H. Sim

Publikováno v: IEEE Transactions on Electron Devices. 53:979-989

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::413d811d056922150a175380ed6e5193
https://doi.org/10.1109/ted.2006.872700

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Integration issues of high-k and metal gate into conventional CMOS technology

Autor: Prashant Majhi, Seung-Chul Song, Craig Huffman, Naim Moumen, J.H. Sim, Paul Kirsch, S.H. Bae, Byoung Hun Lee, Zhibo Zhang

Publikováno v: Thin Solid Films. 504:170-173

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5f26aa1cd7e535e0a71386097c4e3f31
https://doi.org/10.1016/j.tsf.2005.09.080

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Growth mechanism of TiN film on dielectric films and the effects on the work function

Autor: Ken Matthews, Husam N. Alshareef, Huang-Chun Wen, R. Harris, P. Y. Hung, Byoung Hun Lee, H. Luan, Craig Huffman, Prashant Majhi, Kisik Choi, Patrick S. Lysaght, Chris M. Sparks, M. Cruz

Publikováno v: Thin Solid Films. 486:141-144

We have investigated the growth mechanism of ALD-TiN film on different dielectrics and the resulting effective work function value. TiN nucleation rate and growth rate are found to be dependent on the dielectric films. TiN growth mechanism changed fr

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https://doi.org/10.1016/j.tsf.2004.11.239

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STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

Autor: Chang Yong Kang, Kausik Majumdar, Harlan Stamper, Chris Hobbs, Wei-Yip Loh, Saikumar Vivekanand, Craig Huffman, T. Ngai, S. Gausepohl, Rock-Hyun Baek, Martin Rodgers, Ken Matthews, Chien Hao Chen, Paul Kirsch

Publikováno v: IEEE Electron Device Letters. 34:1082-1084

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowi

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https://doi.org/10.1109/led.2013.2271032

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Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

Publikováno v: 2014 IEEE International Electron Devices Meeting.

We report a record low contact resistivity of sub-1.0×10−8 Ω.cm2 realized on n+ In 0.53 Ga 0.47 As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III–V on Si substrates. A novel low-damage III–V

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https://doi.org/10.1109/iedm.2014.7047155

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