Zobrazeno 1 - 10
of 68
pro vyhledávání: '"Contamination delay"'
Autor:
Alfredo Germani, Filippo Cacace
Publikováno v:
Automatica. 85:455-461
In this paper, we consider the control problem of linear systems with state time-delays when the control signal is affected by a possibly time-varying delay. The problem is solved by a chain of predictors under the assumption that a stabilizing contr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::291b28df50fef8f11e406e01b23ae290
https://doi.org/10.1016/j.automatica.2017.08.013
https://doi.org/10.1016/j.automatica.2017.08.013
Publikováno v:
Systems & Control Letters. 89:1-7
This paper proposes an optimal control law for linear systems affected by input delays. Specifically we prove that when the delay functions are known it is possible to generate the optimal control for arbitrarily large delay values by using a DDE wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0469f91bf5b3d4f2469046a6b198b062
https://doi.org/10.1016/j.sysconle.2015.12.003
https://doi.org/10.1016/j.sysconle.2015.12.003
Autor:
Mustak E. Yalcin, Ramazan Yeniceri
Publikováno v:
International Journal of Circuit Theory and Applications. 44:1211-1221
Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doub
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6147f5570559e4fb234ad46fcbcf2225
https://doi.org/10.1002/cta.2158
https://doi.org/10.1002/cta.2158
Publikováno v:
ECCTD
A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2289d27370867810b7e627dd53c0e7cc
https://doi.org/10.1109/ecctd.2017.8093344
https://doi.org/10.1109/ecctd.2017.8093344
Autor:
Pulkit Bhatnagar, Sachin Garg
Publikováno v:
Journal of Electronic Testing. 30:495-504
Transistors within a gate take a finite amount of time to switch and hence there is always a propagation delay associated with it. These delays are evaluated by standard cell characterization techniques using EDA tools. However, these standard measur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2ce89130bc6a06148d05c5cb7268cb3
https://doi.org/10.1007/s10836-014-5469-1
https://doi.org/10.1007/s10836-014-5469-1
Publikováno v:
Analog Integrated Circuits and Signal Processing. 75:435-445
Delay elements are widely used in mixed signal integrated circuits in order to meet design-specific timing requirements. Generally delays are generated by lengthening the transition times of the input signal which is subsequently restored. Slow trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3e017d95cad56dae643e834c2441251
https://doi.org/10.1007/s10470-013-0029-7
https://doi.org/10.1007/s10470-013-0029-7
Publikováno v:
PeerJ Computer Science, Vol 2, p e79 (2016)
Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9f6272dca12130b7516c5bbcaa41b629
https://doi.org/10.7287/peerj.preprints.1412v2
https://doi.org/10.7287/peerj.preprints.1412v2
Publikováno v:
NEWCAS
Delay path reconfiguration is used to control frequency output in Digitally Controlled Oscillators. In order to achieve a very low frequency range, if the delay path is not properly designed, this would result in large area overhead and leakage power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f16603ec8b0dceb4af0e71e14d0afab
https://doi.org/10.1109/newcas.2016.7604821
https://doi.org/10.1109/newcas.2016.7604821
Publikováno v:
2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC).
In the present work different methods for delay causality checking and/or enforcing are described. Group delay, phase delay and front delay concepts are discussed and front delay usage for causality checking is suggested. Front delay is approximated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0de1f91247ac28e8cd5365ff7c3fdec
https://doi.org/10.1109/apemc.2016.7522893
https://doi.org/10.1109/apemc.2016.7522893
Publikováno v:
DATE
As process technology scales down, circuit delay variations become more and more serious due to manufacturing and environmental variations. The delay variations are hardly predictable and thus require additional design margin and impede the chance to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99f4e638cb0852d8b73043c8c18e70d3
https://doi.org/10.3850/9783981537079_0330
https://doi.org/10.3850/9783981537079_0330