Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Conrad H. Ziesler"'
Publikováno v:
IEEE Transactions on Computers. 54:651-659
Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV/sup 2/ rate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff8a8fb397238d4357d3e2c47dae049a
https://doi.org/10.1109/tc.2005.91
https://doi.org/10.1109/tc.2005.91
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:194-207
In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d568aff6f59c6eb1f795d46bf2facd93
https://doi.org/10.1109/tvlsi.2003.810795
https://doi.org/10.1109/tvlsi.2003.810795
Publikováno v:
ISVLSI
In this paper, we present the design and evaluation of a two-phase resonant clock generation and distribution system with layout-extracted inductor parameters in a 0.13/spl mu/m copper process. The design includes a programmable replenishing clock ge
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56ca00ed37f8e51d03b9924f30428e37
https://doi.org/10.1109/isvlsi.2005.74
https://doi.org/10.1109/isvlsi.2005.74
Publikováno v:
ISVLSI
In this paper, we propose boost logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79cd14b327f9e925ea3577219cb97c92
https://doi.org/10.1109/isvlsi.2005.22
https://doi.org/10.1109/isvlsi.2005.22
Autor:
Visvesh S. Sathe, Suhwan Kim, Joohee Kim, Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
Publikováno v:
Conf. Computing Frontiers
Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at sub-stantially lower power dissipation levels than their conventional counterparts. In this paper, we present two such chips
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7a80d70f43012524b427f107c13b4bb
https://doi.org/10.1145/1062261.1062330
https://doi.org/10.1145/1062261.1062330
Publikováno v:
ISLPED
This paper describes Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery, to achieve high energy efficiency at GHz frequencies. The key feature of our design is an energy recovering "boost" stage that prov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42d792d09e2d6f42e1dcba9ea298f558
https://doi.org/10.1145/1077603.1077627
https://doi.org/10.1145/1077603.1077627
Publikováno v:
SoCC
This paper presents an interface technique for hazard-free communication among synchronous intellectual property (IP) cores that belong to different clock domains. By allowing each IP core to run at its most efficient operating point, the proposed in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::debe7a568afbec0911d76fb1b9a1e55b
https://doi.org/10.1109/socc.2004.1362396
https://doi.org/10.1109/socc.2004.1362396
Publikováno v:
ISCAS (2)
Resonant clocking is an attractive alternative to conventional clock distribution due to its significant potential for reducing clocking power. Typically, resonant clock systems rely on sinusoidal clock signals to synchronize flip-flops. Understandin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fc1aecc90bc7098c82555cd2c61b245
https://doi.org/10.1109/iscas.2004.1329255
https://doi.org/10.1109/iscas.2004.1329255
Publikováno v:
ISVLSI
Energy recovery (a.k.a. adiabatic) systems present an attractive alternative to conventional designs due to their significant potential for reducing power. In practical versions of these systems, flip-flops are typically synchronized by a sinusoidal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71d6137a86a1e02fee6268042291a7b0
https://doi.org/10.1109/isvlsi.2004.1339520
https://doi.org/10.1109/isvlsi.2004.1339520
Autor:
Joohee Kim, Conrad H. Ziesler
Publikováno v:
ISVLSI
This paper proposes an energy recovery SRAM that achieves significant dynamic power savings by recovering energy stored in large bit line capacitors. Memory load to power-clock during write is kept fixed by precharging non-selective after each write
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b129ec0d1b3826db1dcf059d39c65ecc
https://doi.org/10.1109/isvlsi.2004.1339522
https://doi.org/10.1109/isvlsi.2004.1339522