Výsledky vyhledávání

Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System

Autor: Haruo Kobayashi, Yudai Abe, Congbing Li, Shogo Katayama, Anna Kuwana

Publikováno v: ASICON

We describe a signal high-frequency estimation circuit using multiple low-frequency sampling circuits following an analog Hilbert filter and analog-to-digital converters (ADCs); here the sampling frequencies are relatively prime. Our proposed system

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8d631a580e31ba9093717aa71b7b6ce7
https://doi.org/10.1109/asicon47005.2019.8983570

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Stochastic TDC Architecture with Self-Calibration and its RTL Verification

Autor: Congbing Li, Haruo Kobayashi, Junshan Wang, Ryoji Shiota

Publikováno v: IEEJ Transactions on Electronics, Information and Systems. 137:335-341

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4e728feda190e2ed9074c94ecca08804
https://doi.org/10.1541/ieejeiss.137.335

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A Glitch-Free Time-to-Digital Converter Architecture Based on Gray Code

Autor: Haruo Kobayashi, Congbing Li

Publikováno v: IEEJ Transactions on Electronics, Information and Systems. 136:22-27

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::126f27fc6e3b59d4867050cff3222b19
https://doi.org/10.1541/ieejeiss.136.22

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Timing measurement BOST architecture with full digital circuit and self-calibration using characteristics variation positively for fine time resolution

Autor: Ryoji Shiota, Congbing Li, Junshan Wang, Haruo Kobayashi

Publikováno v: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

This paper presents a time-to-digital converter (TDC) architecture to measure the timing difference between single-event two pulses with fine time resolution. Its features are as follows: (i) The architecture is based on stochastic process and statis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15301abfaaccf9f133d9058ed7c231d7
https://doi.org/10.1109/ims3tw.2016.7524228

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Successive approximation time-to-digital converter with vernier-level resolution

Autor: Congbing Li, Haruo Kobayashi, Richen Jiang, Mayu Hirano, Kazumi Hatayama, Yuki Ozawa, Nobukazu Tsukiji, Mingcong Yang, Ryoji Shiota

Publikováno v: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional F

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2c5b1b92188be12f829d1ea1eff4d1cf
https://doi.org/10.1109/ims3tw.2016.7524226

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A gray code based time-to-digital converter architecture and its FPGA implementation

Autor: Congbing Li, Haruo Kobayashi

Publikováno v: 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::88b7581d37a889fd5b4ca9d75671029d
https://doi.org/10.1109/rfit.2015.7377926

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Time-to-digital converter architecture with residue arithmetic and its FPGA implementation

Autor: Congbing Li, S. N. Mohyar, Haruo Kobayashi, Shu Wu, Kentaroh Katoh, Junshan Wang

Publikováno v: 2014 International SoC Design Conference (ISOCC).

This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a85dc2761f46524574d30f5f91799688
https://doi.org/10.1109/isocc.2014.7087552

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Experimental verification of timing measurement circuit with self-calibration

Autor: Sato Koshi, Yutaro Kobayashi, Kentaroh Katoh, Takeshi Chujo, Junshan Wang, Congbing Li, Haruo Kobayashi, Daiki Hirabayashi

Publikováno v: 19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings.

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::469d9674bf5b811ae89cc0f0e8e2c765
https://doi.org/10.1109/ims3tw.2014.6997393

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