Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Cong Khieu"'
Autor:
G.K. Konstadinidis, K. Normoyle, null Samson Wong, S. Bhutani, H. Stuimer, T. Johnson, A. Smith, D.Y. Cheung, F. Romano, null Shifeng Yu, null Sung-Hun Oh, V. Melamed, S. Narayanan, D. Bunsey, null Cong Khieu, K.J. Wu, R. Schmitt, A. Dumlao, M. Sutera, null Jade Chau, K.J. Lin, W.S. Coates
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1461-1469
This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5b7fb8bf3a822bbf618554316802a61
https://doi.org/10.1109/jssc.2002.803951
https://doi.org/10.1109/jssc.2002.803951
Autor:
Choon Ping Chng, A.A. Martin, Baoqing Huang, Sourav Ghosh, Xin Liu, S. Zambere, B. Sur, V. Adler, Tan Canh Hoang, N.G. Malur, Marc Tremblay, A. Liebermensch, Suman Kant, Cong Khieu, S. Kumar, F. Chiu, Sung-Hun Oh, Jin Zong, I. Orginos, D. Vo, Yuefei Ge, Hiep Ngo, Allan Tzeng, L. Shih, A. Kowalczyk, Lan Lee, W.J. de Lange, Y.S. Kao, C. Amir
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1609-1616
The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8f44a1fd32847413217e2c63d26f406
https://doi.org/10.1109/4.962280
https://doi.org/10.1109/4.962280
Autor:
G. Konstadinidis, K. Normoyle, S. Wong, S. Bhutani, H. Stuimer, T. Johnson, A. Smith, D. Cheung, F. Romano, null Shifeng Yu, null Sung-Hun Oh, V. Melamed, S. Narayanan, D. Bunsey, null Cong Khieu, K.J. Wu, R. Schmitt, A. Dumlao, M. Sutera, null Jade Chau, K.J. Lin
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::82e3c2f1e930d136ff7cb9fa505a7b0a
https://doi.org/10.1109/isscc.2002.993070
https://doi.org/10.1109/isscc.2002.993070
Autor:
C. Amir, D. Vo, D. Pini, A. Kowalczyk, Xin Liu, Sung-Hun Oh, Baoqing Huang, V. Adler, S. Kumar, Sourav Ghosh, Lan Lee, B. Sur, Allan Tzeng, N.G. Malur, Yuefei Ge, Chung Lau, W.J. de Lange, S. Zambare, Y.S. Kao, Cong Khieu, Jin Zong, F. Chiu, A. Liebermensch, Tan Hoang, S. Dubler, I. Orginos, Choon Chug, L. Shih, R. Hu, Suman Kant, Hiep Ngo
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cc9093764d1aa84e731202d34375288
https://doi.org/10.1109/isscc.2001.912619
https://doi.org/10.1109/isscc.2001.912619
Autor:
Konstadinidis, G., Normoyle, K., Wong, S., Bhutani, S., Stuimer, H., Johnson, T., Smith, A., Cheung, D., Romano, F., Shifeng Yu, Sung-Hun Oh, Melamed, V., Narayanan, S., Bunsey, D., Cong Khieu, Wu, K.J., Schmitt, R., Dumlao, A., Sutera, M., Jade Chau
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315); 2002, p270-502, 233p
Autor:
Konstadinidis, Georgios K., Normoyle, Kevin, Wong, Samson, Bhutani, Sutikshan, Stuimer, Harry, Johnson, Timothy, Smith, Alan, Cheung, Daniel Y., Romano, Fabrizio, Shifeng Yu, Sung-Hun Oh, Melamed, Victor, Narayanan, Sridhar, Bunsey, David, Cong Khieu, Wu, Kevin J., Schmitt, Ralf, Dumlao, Andy
Publikováno v:
IEEE Journal of Solid-State Circuits; Nov2002, Vol. 37 Issue 11, p1461, 9p, 20 Black and White Photographs, 8 Diagrams, 1 Chart, 1 Graph
Autor:
Kowalczyk, A., Adler, V., Amir, C., Chiu, F., Choon Ping Chng, De Lange, W.J., Yuefei Ge, Ghosh, S., Tan Canh Hoang, Baoqing Huang, Kant, S., Kao, Y.S., Cong Khieu, Kumar, S., Lan Lee, Liebermensch, A., Xin Liu, Malur, N.G., Martin, A.A., Ngo, H.
Publikováno v:
IEEE Journal of Solid-State Circuits; Nov2001, Vol. 36 Issue 11, p1609-1616, 8p
Autor:
Joshi, V., Cong Khieu, Smith, C.G., Schepens, C., Csaszar, F., Lacey, D., Nagata, T., Renault, M., Van Kampen, R., Knipe, R., Yost, D.
Publikováno v:
Interconnect Technology Conference (IITC), 2010 International; 2010, p1-3, 3p
Autor:
Kowalczyk, A., Adler, V., Amir, C., Chiu, F., Choon Chug, De Lange, W., Dubler, S., Yuefei Ge, Ghosh, S., Tan Hoang, Hu, R., Baoqing Huang, Kant, S., Kao, Y.S., Cong Khieu, Kumar, S., Chung Lau, Lan Lee, Liebermensch, A., Xin Liu
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177); 2001, p236-451, 3p