Zobrazeno 1 - 10
of 559
pro vyhledávání: '"Comparator applications"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:426-430
In this brief, we design a single-channel 5-bit 500-MS/s asynchronous digital slope analog-to-digital converter. It is implemented and simulated in SMIC 55-nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used, which can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a062e86f0f4b3967e00e6d42878b3a76
https://doi.org/10.1109/tcsii.2017.2695720
https://doi.org/10.1109/tcsii.2017.2695720
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:458-470
In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, misma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b2b6fdb81c0141158a61176a6b76438
https://doi.org/10.1109/tcsi.2017.2723799
https://doi.org/10.1109/tcsi.2017.2723799
Publikováno v:
AEU - International Journal of Electronics and Communications. 81:163-170
In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e65162d12315673ffb79e834428bc7e
https://doi.org/10.1016/j.aeue.2017.07.018
https://doi.org/10.1016/j.aeue.2017.07.018
Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator
Autor:
Vijay Savani, Niranjan M. Devashrayee
Publikováno v:
Analog Integrated Circuits and Signal Processing. 93:287-298
The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this pap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::464b7188f85e4d0db20489d10f471e01
https://doi.org/10.1007/s10470-017-1040-1
https://doi.org/10.1007/s10470-017-1040-1
Autor:
Gholamreza Moradi, Mehran Shamaiee, Mohammad Saeid Ghaffarian, Somayeh Khajepour, Mohammad Mahdi Honari
Publikováno v:
IET Microwaves, Antennas & Propagation. 11:1726-1733
A novel wideband planar single layer mono-pulse comparator for the application of mono-pulse angle of arrival and target detecting is presented. This low cost comparator consists of three new broadband differential phase shifters and four 3 dB hybrid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2977ed904f35e214a7508db767aba179
https://doi.org/10.1049/iet-map.2016.0927
https://doi.org/10.1049/iet-map.2016.0927
Autor:
Waldemar Jendernalik
Publikováno v:
Circuits, Systems, and Signal Processing. 36:4829-4843
This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec3c34543bca5011e23753e5dd95f671
https://doi.org/10.1007/s00034-017-0630-6
https://doi.org/10.1007/s00034-017-0630-6
Autor:
Rachna Arya, Hemlata Gururani
Publikováno v:
International Journal of Energy Technology and Management. 1:15-22
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1c0d21e49e679a78d186d0ee0df92d8
https://doi.org/10.21742/ijetm.2017.1.1.03
https://doi.org/10.21742/ijetm.2017.1.1.03
Autor:
Sanmukh Kaur, Anupama Prakash
Publikováno v:
Journal of Optics. 47:104-109
High-speed all-optical logic circuits have attracted much attention because of their important roles in signal processing in next-generation optical networks. We demonstrate an all-optical two bit comparator using an optical gate architecture based o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05fcf993793decf8cd0eb52f495956bc
https://doi.org/10.1007/s12596-017-0421-2
https://doi.org/10.1007/s12596-017-0421-2
Autor:
Zia Daei Kuzekanani, Adib Abrishamifar, Tohid Moradi Khanshan, Mozhdeh Nematzadeh, Saeed Naghavi, Niloofar Sharifi, Jafar Sobhi
Publikováno v:
Analog Integrated Circuits and Signal Processing. 92:233-245
A fully differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a positive feedback or latch stage and the offset cancellation circuitry. The effect of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b61d09aa78e88b5e51450f3b09c9c58
https://doi.org/10.1007/s10470-017-0998-z
https://doi.org/10.1007/s10470-017-0998-z
Publikováno v:
AEU - International Journal of Electronics and Communications. 76:125-131
This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cabf651347d45bebf7e9a8c37c14fd74
https://doi.org/10.1016/j.aeue.2017.04.004
https://doi.org/10.1016/j.aeue.2017.04.004