Výsledky vyhledávání - "Colita Parker"

Ultra-Thin Resists for Advanced Lithography

Autor: Jonathan L. Cobb, Richard D. Peters, Colita Parker

Publikováno v: Journal of Photopolymer Science and Technology. 17:465-473

The continuous reduction of feature sizes in integrated circuits (IC) is driving the development of advanced lithographic techniques that enable patterning of sub-100-nm features with good fidelity and process margins. Requirements for printing these

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c1f01e459f8e852c6ffa99bce996bced
https://doi.org/10.2494/photopolymer.17.465

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Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Publikováno v: Scopus-Elsevier

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a4374c45132a6872abaa958490fd0c29
https://doi.org/10.1109/istdm.2006.1716039

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Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS

Publikováno v: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0d8b5c6294636148e63fcac464110237
https://doi.org/10.1109/iedm.2005.1609452

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ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET

Publikováno v: 2006 IEEE International Conference on IC Design and Technology.

The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET dev

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad3751852ced118a2c2cf9d8f5e511e
https://doi.org/10.1109/icicdt.2006.220809

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Applications of CPL mask technology for sub-65nm gate imaging

Autor: Jonathan L. Cobb, Richie Peters, Jungchul Park, Wei Wu, Lloyd C. Litt, Will Conley, Bryan S. Kasprowicz, Doug Van Den Broeke, Ramkumar Karur-Shanmugam, Colita Parker

Publikováno v: Optical Microlithography XVIII.

The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1e18706c9a172ae75b5603ee112cb5f5
https://doi.org/10.1117/12.600912

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Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination

Autor: Patrick Montgomery, S. Filipiak, Danny Babbitt, Richard Peters, Cesar Garza, Colita Parker, Jonathan L. Cobb, Bill Darlington

Publikováno v: SPIE Proceedings.

Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm 1 . In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c7d8306ea1b922c8e5f75e87076e2c85
https://doi.org/10.1117/12.600785

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CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

Publikováno v: 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simul

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::59ac5cac943ae0426e0d7018a8c20627
https://doi.org/10.1109/soi.2004.1391610

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CPL reticle technology for advanced device applications

Publikováno v: SPIE Proceedings.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::99543ba0f834e728f64750bda13b0033
https://doi.org/10.1117/12.557802

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Multi gated device architectures advances, advantages and challenges

Autor: A. Vandooren, R. Shimer, Bruce E. White, Bich-Yen Nguyen, R. Mora, Michael A. Sadd, S. Jallepalli, J. Hughes, S. Kalpai, D. Sing, Yang Du, G. Workman, A. Mogab, Raghav Rai, Tab A. Stephens, Colita Parker, M. Zavala, Aaron Thean, Leo Mathew

Publikováno v: 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::99ac145f7ce4fcae65b1bbbd8485a55a
https://doi.org/10.1109/icicdt.2004.1309916

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