Zobrazeno 1 - 10
of 320
pro vyhledávání: '"Cmos scaling"'
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1184-1192 (2020)
Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various
Externí odkaz:
https://doaj.org/article/db8c3b3bb6fc4c59b05c969bef027e09
Autor:
Phil Oldiges, Reinaldo A. Vega, Henry K. Utomo, Nick A. Lanzillo, Thomas Wassick, Juntao Li, Junli Wang, Ghavam G. Shahidi
Publikováno v:
IEEE Access, Vol 8, Pp 154329-154337 (2020)
The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This article looks at the power-performance benefit of the 10/7nm node as compared to the previous node (14nm). Specifically, we trac
Externí odkaz:
https://doaj.org/article/e6542f6bb5bb48d6853138be62d717de
Autor:
Ghavam G. Shahidi
Publikováno v:
IEEE Access, Vol 7, Pp 851-856 (2019)
This paper tracks the scaling of total chip power at constant frequency (i.e., energy-per-operation) through the last few CMOS nodes. The focus is on high-performance microprocessors. To evaluate the progression of chip power, Intel’s Core-i7 (Inte
Externí odkaz:
https://doaj.org/article/4ad99db948654c908a6a165c98a0fb07
Akademický článek
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Autor:
Sheng-Kai Su, Alfonso Sanchez-Soares, Edward Chen, Thomas Kelly, Giorgos Fagas, James C. Greer, Gregory Pitner, H.-S. Philip Wong, Iuliana P. Radu
Publikováno v:
IEEE Electron Device Letters. 43:1367-1370
Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scali
Publikováno v:
IEEE Design & Test. 38:28-35
The advancements of the Internet of Things (IoT) and Artificial Intelligence (AI) have resulted in the proliferation of intelligent computing devices. However, AI-based solutions are often compute-intensive, severely limiting the performance of edge
Publikováno v:
Silicon. 13:3681-3690
CMOS scaling is the approach to accomplish the VLSI goals in the past decades. The existing CMOS technology is facing challenges related to short channel effects and reached to its performance limits at sub-10 nm technology nodes. The negative capaci
Akademický článek
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Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1184-1192 (2020)
Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.