Zobrazeno 1 - 10
of 1 925
pro vyhledávání: '"Clock domain crossing"'
Publikováno v:
Xibei Gongye Daxue Xuebao, Vol 40, Iss 2, Pp 369-376 (2022)
There are a large number of multi-clock domain circuits in the airborne equipment of aircraft. When data is transmitted across the clock domain, meta-stability may occur, resulting in data transmission errors and reduced circuit reliability. However,
Externí odkaz:
https://doaj.org/article/e9e531281ea14b48b0e561cbe67e527e
Publikováno v:
Journal of Electrical and Electronics Engineering, Vol 14, Iss 2, Pp 19-24 (2021)
Moore‘s law has been motivating the semiconductor industry to churn out multi-clock (mostly unrelated) complex system on chip (SoC) designs. Data/signals that crosses such unrelated or asynchronous clock domains are more likely to be sampled before
Externí odkaz:
https://doaj.org/article/99957a07be1b4f35a24ed5a93b8c9b6e
Akademický článek
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Akademický článek
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Akademický článek
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Publikováno v:
IEEE Transactions on Applied Superconductivity. 30:1-8
Digital single-flux quantum (SFQ) technology promises to meet the demands of ultralow-power and high-speed computing needed for future exascale supercomputing systems. However, high degrees of variability makes ultrahigh-speed low-skew clock distribu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8569880ac25c36fcec5d94cbc4fcf67
https://doi.org/10.1109/tasc.2020.2997260
https://doi.org/10.1109/tasc.2020.2997260
Publikováno v:
Tongxin xuebao, Vol 33, Pp 151-158 (2012)
Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from fu
Externí odkaz:
https://doaj.org/article/70982c73881e439895cfe97f0f8160a1
Autor:
Vaibbhav Taraate
Publikováno v:
Digital Logic Design Using Verilog ISBN: 9789811631986
Digital Logic Design Using Verilog ISBN: 9788132227892
Digital Logic Design Using Verilog ISBN: 9788132227892
In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cce9f9d114b2da6d389be8202bbf3127
https://doi.org/10.1007/978-981-16-3199-3_22
https://doi.org/10.1007/978-981-16-3199-3_22
Autor:
Artak Kirakosyan, Stepan Harutyunyan, Vardan Amiryan, Arsen Momjyan, Vazgen Melikyan, Taron Kaplanyan
Publikováno v:
EWDTS
A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the number of flops. In high-frequency
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0781a3773982b393476d528ebc2baa8b
https://doi.org/10.1109/ewdts52692.2021.9580985
https://doi.org/10.1109/ewdts52692.2021.9580985
Autor:
Muhammad Ziad Muhammad Ghazy, Medhat Ashraf Alhaddad, Abanoub Ghadban Helmy, Seif Eldin Mohamed Hussein, Nagy Raouf Nagy, Ahmed H. Yousef
Publikováno v:
2021 8th International Conference on Signal Processing and Integrated Networks (SPIN).
Verification is an important part of the Electronic Design Automation (EDA) design flow which currently takes a considerable amount of time. During the synthesis process, Different optimizations are done to the Register-Transfer-Level (RTL) code to o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ba7928ff19e168017ef857034e8ca54
https://doi.org/10.1109/spin52536.2021.9566070
https://doi.org/10.1109/spin52536.2021.9566070