Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Clifford Ting"'
Autor:
Syed Rubab, James Guthrie, Jing Wang, Clifford Ting, Ruslana Shulyzki, Aynaz Vatankhahghadim, Michael De Vita, Alireza Parsafar, Junhong Zhao, Noam Dolev, Sitaraman V. Iyer, Bahram Zand, Aleksey Tyshchenko, Mike Bichan, Eric Liu, Fulvio Spagna, Shaham Sharifian, Katya Tyshchenko
Publikováno v:
CICC
This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and
Autor:
Clifford Ting, Mohammad Sadegh Jalali, Masaya Kibune, Joshua Liang, Hirotaka Tamura, Ali Sheikholeslami
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1658-1667
This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3x the baud rate. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the
Autor:
Masaya Kibune, Joshua Liang, Ali Sheikholeslami, Clifford Ting, Mohammad Sadegh Jalali, Hirotaka Tamura, N. Kovacevic
Publikováno v:
Electronics Letters. 51:551-553
The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equ
Publikováno v:
CICC
This paper proposes replacing the analog phase interpolator in a phase-tracking ADC-based receiver with a digital data interpolator following the ADC. This allows for a blind ADC-based receiver that has a simpler adaptive DFE compared to previous imp
Autor:
Ali Sheikholeslami, M. Sadegh Jalali, Clifford Ting, Hirotaka Tamura, Behrooz Abiri, Masaya Kibune
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by
Publikováno v:
ISSCC
ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that t
Publikováno v:
ISSCC
The use of adaptive equalizers at the front end of receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requi