Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Clemens Schlachta"'
Autor:
Manfred Glesner, Clemens Schlachta
Publikováno v:
Advances in Radio Science, Vol 1, Pp 223-228 (2003)
One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an ene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1112b3e9e70f2f7ba2dae12bd91b9cf4
https://www.adv-radio-sci.net/1/223/2003/
https://www.adv-radio-sci.net/1/223/2003/
Publikováno v:
Mechatronics. 12:1047-1057
For the online measurement of erosive cavitation aggressiveness in hydraulic turbomachinery a system is developed, which is based on the measurement of the structure born noise. The direct coupling of the piezoelectric sensor on the exposed impeller
Publikováno v:
FPL
This paper presents the realisation of a hardware-in-the-loop system to investigate the performance of different cellular automata (CA) structures. The system is applied to regular lattice CAs and to small-world CAs, which are expected to expose bett
Autor:
Clemens Schlachta, Leandro Soares Indrusiak, Manfred Glesner, A. Garcia, M. Petrov, T. Murugan, Ricardo Reis
Publikováno v:
SBCCI
Scopus-Elsevier
Scopus-Elsevier
With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose severe difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in lon
Publikováno v:
FPT
This paper focuses on the reconfiguration requirements of hardware platforms for high speed wireless communication systems. Due to the underlying trade-off between flexibility and efficiency, many reconfigurable hardware solutions and FPGA implementa
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540230953
PATMOS
PATMOS
This work analyses the effects on timing and power consumption of the inductive coupling in long high-frequency on-chip interconnects. By means of extensive simulations it is shown that the common assumptions used until now when considering only line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2eda1cb0dd269991b9cfa848770e4acb
https://doi.org/10.1007/978-3-540-30205-6_84
https://doi.org/10.1007/978-3-540-30205-6_84