Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Claudiu Zissulescu"'
Autor:
Claudiu Zissulescu, Ed F. Deprettere, Shuvra S. Bhattacharyya, Ming-Yung Ko, Sebastian Puthenpurayil, Bart Kienhuis
Publikováno v:
IEEE Transactions on Signal Processing. 55:3126-3138
In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ffe9169e8487cda4407bc3ed52274d1
https://doi.org/10.1109/tsp.2007.893964
https://doi.org/10.1109/tsp.2007.893964
Autor:
Hristo Nikolov, Ed F. Deprettere, Simon Polstra, Mark Thompson, R. Bose, Claudiu Zissulescu, Todor Stefanov, Andy D. Pimentel
Publikováno v:
DAC
Proceedings of the 45th annual conference on design automation, 574-579
STARTPAGE=574;ENDPAGE=579;TITLE=Proceedings of the 45th annual conference on design automation
Proceedings of the 45th annual conference on design automation, 574-579
STARTPAGE=574;ENDPAGE=579;TITLE=Proceedings of the 45th annual conference on design automation
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which design space exploration (DSE), system-level synthesis, application map
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4412fad552b803be4d8acba343653f89
https://doi.org/10.1145/1391469.1391615
https://doi.org/10.1145/1391469.1391615
Publikováno v:
ASAP
The COMPAAN/LAURA (Stefanov et al., 2004) tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a process network in which the control is parameter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d78545dae82635af92fe9d43b5ada041
https://doi.org/10.1109/asap.2005.34
https://doi.org/10.1109/asap.2005.34
Publikováno v:
ASAP
This paper is concerned with the compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6529225252a5b75c54d65f6799ba70be
https://doi.org/10.1109/asap.2006.51
https://doi.org/10.1109/asap.2006.51
Publikováno v:
FPL
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, imaging, or multimedia) written in a subset of Matlab onto reconfigurable devices. This design methodology is implemented
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f644ead91e729742e76b93c55f69747e
https://doi.org/10.1109/fpl.2005.1515748
https://doi.org/10.1109/fpl.2005.1515748
Publikováno v:
Cristea, M-L, Zissulescu, C, Deprettere, E & Bos, H J 2005, FPL-3E: towards language support for reconfigurable packet processing . in Proceedings of SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Lecture Notes in Computer Science, Vol.3553/2005, ISSN 0302-9743 . Samos, Greece .
Lecture Notes in Computer Science ISBN: 9783540269694
SAMOS
Vrije Universiteit Amsterdam
Scopus-Elsevier
Proceedings of SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Lecture Notes in Computer Science, Vol.3553/2005, ISSN 0302-9743
Lecture Notes in Computer Science ISBN: 9783540269694
SAMOS
Vrije Universiteit Amsterdam
Scopus-Elsevier
Proceedings of SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Lecture Notes in Computer Science, Vol.3553/2005, ISSN 0302-9743
The FPL-3e packet filtering language incorporates explicit support for reconfigurable hardware into the language. FPL-3e supports not only generic header-based filtering, but also more demanding tasks such as payload scanning and packet replication.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4f1021dca101c01995e9884eb8957dc4
https://hdl.handle.net/1871.1/873d49f5-ac1b-4d15-a920-a032f0a4f370
https://hdl.handle.net/1871.1/873d49f5-ac1b-4d15-a920-a032f0a4f370
Publikováno v:
Field Programmable Logic and Application ISBN: 9783540229896
FPL
FPL
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platforms, such as FPGAs, using IP cores to implement the data-path of the a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c13a19f934a823279a244544736bac39
https://doi.org/10.1007/978-3-540-30117-2_70
https://doi.org/10.1007/978-3-540-30117-2_70
Publikováno v:
Field Programmable Logic and Application ISBN: 9783540408222
FPL
FPL
At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto reconfigurable platforms. In this chain, first the Matlab code is converted au
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8990e0b69e85feda53766fa2aebb3aff
https://doi.org/10.1007/978-3-540-45234-8_88
https://doi.org/10.1007/978-3-540-45234-8_88
Publikováno v:
International Journal of Embedded Systems. 3:170
The Compaan/Laura tool chain allows efficient mapping of signal processing applications written in Matlab onto reconfigurable platforms. In this chain, the Matlab code is converted into a Kahn Process Network model, which serves as input to a hardwar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ea301eaa63373a84b2562e43cb2957f
https://doi.org/10.1504/ijes.2008.020298
https://doi.org/10.1504/ijes.2008.020298