Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Claudio Mucci"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:3043-3052
Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs
Publikováno v:
ICECS
This paper proposes a reconfigurable System-on-Chip (SoC) for Smart-Power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b7788460a572436281f680fc1d06f0d5
http://hdl.handle.net/11585/663403
http://hdl.handle.net/11585/663403
Autor:
Claudio Mucci, Roberto Guerrieri, Matteo Pizzotti, Roberto Canegallo, Davide Rossi, Luca Perugini
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1990-2003
The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale int
Autor:
Francesco Renzini, Eleonora Franchi Scarselli, Claudio Mucci, Matteo Cuppini, Roberto Canegallo
Publikováno v:
Electronics, Vol 8, Iss 3, p 272 (2019)
Electronics
Volume 8
Issue 3
Electronics
Volume 8
Issue 3
This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully s
This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4e7b65759f614d485f3d8596897a95bc
http://hdl.handle.net/11585/472169
http://hdl.handle.net/11585/472169
Autor:
Fabio Campi, Tapani Ahonen, J. Kylliainen, Fabio Garzia, Claudio Brunelli, Jari Nurmi, Claudio Mucci, Davide Rossi
Publikováno v:
Journal of Systems Architecture. 54:1143-1154
This paper describes an open-source and highly scalable floating-point unit (FPU) for embedded systems. Our FPU is fast and efficient, due to the high parallelism of its architecture: the functional units inside the datapath can operate in parallel a
Autor:
Michael Hübner, Tommaso DeMarco, Florian Ries, Antonio Marcello Coppola, Jürgen Becker, Matthias Kühnle, Riccardo Locatelli, Claudio Mucci, Giuseppe Maruccia, Fabio Campi, A. Deledda, Lorenzo Pieralisi
Publikováno v:
IEEE Design & Test of Computers. 25:442-451
Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On
Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::958062ed42316c7090c058042d58d8fd
http://hdl.handle.net/11585/192529
http://hdl.handle.net/11585/192529
Autor:
Roberto Guerrieri, Davide Rossi, Henning Sahlbach, Fabio Campi, W. Putzke-Roming, Claudio Mucci, Sean Whitty, Simone Spolzino, Luca Vanzolini, Rolf Ernst
This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granula
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7673186326f2b9b8937aead03210f355
http://hdl.handle.net/11585/126393
http://hdl.handle.net/11585/126393
Autor:
Sean Whitty, A. Deledda, Jürgen Becker, S. Guyetant, Fabio Campi, Rolf Ernst, Davide Rossi, Wolfram Putzke-Roeming, Michael Hübner, S. Chevobbe, S. Pucillo, Claudio Mucci, Matthias Kühnle
Publikováno v:
SoC
Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-grained reconfig