Zobrazeno 1 - 10
of 88
pro vyhledávání: '"Claude Tabone"'
Autor:
Gerard Billiot, Paul Mattei, Bogdan Vysotskyi, Adrien Reynaud, Louis Hutin, Christophe Plantier, Emmanuel Rolland, Marc Gely, Giulia Usai, Claude Tabone, Gael Pillonnet, Stephanie Robinet, Sebastien Hentz
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d5fdeaa302437eae6f0abcbf614d6f8
https://doi.org/10.1109/isscc42614.2022.9731729
https://doi.org/10.1109/isscc42614.2022.9731729
Autor:
Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018
https://hal.archives-ouvertes.fr/hal-03434018
Autor:
Pascale Boulanger, Guillaume Jourdan, Thomas Alava, Louise Banniard, C. Plantier, Patrick Villard, Emmanuel Rolland, Giulia Usai, Pierre Etienne Allain, Alexandre Fafin, Olivier Castany, Eduardo Gil Santos, Claude Tabone, Louis Hutin, Sebastien Hentz, Ariel Brenac, Sergio Dominauez-Medina, Paul Mattei, Charlie Barrois, Shawn Fostner, Ivan Favero, Martial Defoort, Marc Sansa, Thomas Ernst, Ujwol Palanchoke, Marc Gely, Gerard Billiot, Maxime Hermouet, Emeline Vernhes, Caroline Fontelaye, Guillaume Nonglaton, Christophe Masselon
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM)
2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, United States. pp.12.4.1-12.4.3, ⟨10.1109/IEDM.2018.8614532⟩
2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, France. pp.12.4.1-12.4.3
2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, United States. pp.12.4.1-12.4.3, ⟨10.1109/IEDM.2018.8614532⟩
2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, France. pp.12.4.1-12.4.3
International audience; The first Very Large Scale Integration process with variable shape beam lithography for optomechanical devices is presented. State of the art performance was obtained with silicon microdisk resonators showing 1 million optical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d247b1cea92641ebe689569b0559d70c
https://hal.science/hal-02284178
https://hal.science/hal-02284178
Autor:
Eugénie Martinez, Pushpendra Kumar, Jean-Michel Pedini, Florian Domengie, F. Gaillard, Charles Leroux, Denis Guiheux, Claude Tabone, Gerard Ghibaudo, Virginie Loup, Yves Morand
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
In this paper, we present for the first time specific methodology and test structures authorizing an accurate analysis of XPS under bias measurements. Such analysis which identifies effective biasing across the device, allows to determine the absolut
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00406df9a7d362b9445cd339472b7df7
https://doi.org/10.1109/iedm.2018.8614554
https://doi.org/10.1109/iedm.2018.8614554
Autor:
Carlos Mazure, Bich-Yen Nguyen, Phuong Nguyen, Maud Vinet, Louis Hutin, J. Pelloux-Prayer, Christian Arvet, Nicolas Bernier, M. Casse, Claude Tabone, Oliver Faynot, S. Barraud, Jean-Michel Hartmann, Christophe Maleville, Ludovic Ecarnot
Publikováno v:
ECS Transactions. 75:59-65
We present for the first time the successful fabrication of Ω-gate P-type FETs with epitaxial compressively-strained SiGe (Ge=30%) on tensily-strained SOI substrates. The recess down to the strained-Si etch-stop layer in the source/drain (S/D) areas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4f519ad738ffb2ba354bac254437ffb
https://doi.org/10.1149/07508.0059ecst
https://doi.org/10.1149/07508.0059ecst
Autor:
Sebastien Martinie, Claude Tabone, C. Le Royer, Louis Hutin, J. Borrel, M. Vinet, R. P. Oeflein
Publikováno v:
Solid-State Electronics. 115:160-166
In this paper, we study the ambipolar tunneling signature from the output characteristics of TFETs featuring Si 0.8 Ge 0.2 homojunctions, which we compare to those measured on conventional MOSFETs and Schottky Barrier FETs. The difference with the fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45ba62c801524f1be62ad8fb82160263
https://doi.org/10.1016/j.sse.2015.08.007
https://doi.org/10.1016/j.sse.2015.08.007
Autor:
J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup
Publikováno v:
2017 IEDM Technical Digest
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. pp.32.2.1-32.2.4, ⟨10.1109/IEDM.2017.8268484⟩
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. pp.32.2.1-32.2.4, ⟨10.1109/IEDM.2017.8268484⟩
session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f667185abf93ecbc97dd4a441fb34f4d
https://hal.archives-ouvertes.fr/hal-01959097
https://hal.archives-ouvertes.fr/hal-01959097
Autor:
Gerard Ghibaudo, Claude Tabone, Emmanuel Josse, Joris Lacord, Franck Arnaud, Remy Berthelon, M. Vinet, Yann-Michel Niquet, C. Le Royer, L. Bourdet, Denis Rideau, Didier Dutartre, O. Rozeau, F. Andneu, Pascal Nguyen, Alain Claverie, M. Casse, S. Barraud, François Triozon
Publikováno v:
2017 VLSI-Technology Technical Digest
2017 IEEE Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩
2017 Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩
2017 Symposium on VLSI Technology
session 17: CMOS integration; International audience; We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e7a44e250cbeeaa54e79eb88b0ad7d87
https://hal.archives-ouvertes.fr/hal-02050220
https://hal.archives-ouvertes.fr/hal-02050220
Autor:
J. Micoud, C.-M. V. Lu, Maud Vinet, Charles Leroux, Xavier Federspiel, R. Gassilloud, Perrine Batude, Laurent Brunet, Vincent Delaye, G. Romano, L. Pasini, Xavier Garros, F. Deprat, Claude Tabone, D. Nouguier, N. Rambal, Bernard Previtali, P. Besombes, D. Ney, D. Barge, Francois Andrieu, A. Toffoli, M.-P. Samson, Thomas Skotnicki, A. Tsiara, Claire Fenouillet-Beranger
Publikováno v:
2017 Symposium on VLSI Technology.
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a458fe92975cbc00a812ba23ee9a940
https://doi.org/10.23919/vlsit.2017.7998181
https://doi.org/10.23919/vlsit.2017.7998181
Autor:
X. Garros, N. Rambal, C. Fenouillet-Beranger, M. Brocard, L. Pasini, G. Cibrario, Thomas Skotnicki, M.-P. Samson, A. Ayres, Laurent Brunet, M. Vinet, C. Tallaron, C-M. V., O. Billoint, R. Gassilloud, Francois Andrieu, R. Kies, G. Romano, Perrine Batude, Bernard Previtali, A. Toffoli, M. Casse, P. Besombes, C. Leroux, Claude Tabone, V. Lapras, A. Laurent, D. Barge
Publikováno v:
2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f5a2b330e51e3a5752e754ac6b9e197
https://doi.org/10.1109/vlsi-tsa.2017.7942495
https://doi.org/10.1109/vlsi-tsa.2017.7942495