Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Claire Maiza"'
Publikováno v:
RTSS
2020 IEEE Real-Time Systems Symposium (RTSS)
2020 IEEE Real-Time Systems Symposium (RTSS), Dec 2020, Houston, TX, United States. ⟨10.1109/RTSS49844.2020.00034⟩
Proceedings-Real-Time Systems Symposium
2020 IEEE Real-Time Systems Symposium (RTSS)
2020 IEEE Real-Time Systems Symposium (RTSS), Dec 2020, Houston, TX, United States. ⟨10.1109/RTSS49844.2020.00034⟩
Proceedings-Real-Time Systems Symposium
We study the implementation of data- flow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We f
Publikováno v:
DATE 2020-Design, Automation and Test in Europe Conference
DATE 2020-Design, Automation and Test in Europe Conference, Mar 2020, Grenoble, France. pp.1-4
DATE
DATE 2020-Design, Automation and Test in Europe Conference, Mar 2020, Grenoble, France. pp.1-4
DATE
In RTNS 2016, Rihani et al. [7] proposed an algorithm to compute the impact of interference on memory accesses on the timing of a task graph. It calculates a static, time-triggered schedule, i.e. a release date and a worst-case response time for each
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7108e6aa979024a42c7b320aee7718d5
https://hal.archives-ouvertes.fr/hal-02431273/document
https://hal.archives-ouvertes.fr/hal-02431273/document
Publikováno v:
RTNS 2019-27th International Conference on Real-Time Networks and Systems
RTNS 2019-27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩
RTNS
RTNS 2019-27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩
RTNS
We consider hard real-time applications running on many-core processor containing several clusters of cores linked by a Network-on-Chip (NoC). Communications are done via shared memory within a cluster and through the NoC for inter-cluster communicat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::487430f9c8f95d2967ed441ebd1910d4
https://hal.science/hal-02320463/file/rtns2019.pdf
https://hal.science/hal-02320463/file/rtns2019.pdf
Publikováno v:
Proceedings of the ACM on Programming Languages
Proceedings of the ACM on Programming Languages, ACM, 2019, 3 (POPL), ⟨10.1145/3290367⟩
Proceedings of the ACM on Programming Languages, 2019, 3 (POPL), ⟨10.1145/3290367⟩
Proceedings of the ACM on Programming Languages, ACM, 2019, 3 (POPL), ⟨10.1145/3290367⟩
Proceedings of the ACM on Programming Languages, 2019, 3 (POPL), ⟨10.1145/3290367⟩
For applications in worst-case execution time analysis and in security, it is desirable to statically classify memory accesses into those that result in cache hits, and those that result in cache misses. Among cache replacement policies, the least re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59d555de8235e429b7521eef5043d0cb
https://hal.archives-ouvertes.fr/hal-01908648
https://hal.archives-ouvertes.fr/hal-01908648
Autor:
Hamza Rihani, Claire Maiza, Robert I. Davis, Joël Goossens, Juan M. Rivas, Sebastian Altmeyer
Publikováno v:
ACM computing surveys, 52 (3
ACM Computing Surveys, 52(3):56. Association for Computing Machinery (ACM)
ACM Computing Surveys, 52(3):56. Association for Computing Machinery (ACM)
This survey provides an overview of the scientific literature on timing verification techniques for multi-core real-time systems. It reviews the key results in the field from its origins around 2006 to the latest research published up to the end of 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::125c8b02218807f52e81572ff8b3ec21
https://opus.bibliothek.uni-augsburg.de/opus4/files/69694/69694.pdf
https://opus.bibliothek.uni-augsburg.de/opus4/files/69694/69694.pdf
Autor:
Robert I. Davis, Vincent Nélis, Jan Reineke, Leandro Soares Indrusiak, Claire Maiza, Sebastian Altmeyer
Publikováno v:
Real-Time Systems, 54(3). Springer Netherlands
Repositório Científico de Acesso Aberto de Portugal
Repositório Científico de Acesso Aberto de Portugal (RCAAP)
instacron:RCAAP
Repositório Científico de Acesso Aberto de Portugal
Repositório Científico de Acesso Aberto de Portugal (RCAAP)
instacron:RCAAP
In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands plac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ac6c8f956f51116e8436eb45a17ff464
https://dare.uva.nl/personal/pure/en/publications/an-extensible-framework-for-multicore-response-time-analysis(a926c998-ce00-4270-b3be-863f72e5fda4).html
https://dare.uva.nl/personal/pure/en/publications/an-extensible-framework-for-multicore-response-time-analysis(a926c998-ce00-4270-b3be-863f72e5fda4).html
Publikováno v:
Real-Time Systems. 51:192-220
Real-time critical systems can be considered as correct if they compute both right and fast enough. Functionality aspects (computing right) can be addressed using high level design methods, such as the synchronous approach that provides languages, co
Autor:
Pascal Richard, Joël Goossens, Claire Maiza, Thomas Chapeaux, Laurent George, Guillaume Phavorin
Publikováno v:
Real-Time Systems
Real-Time Systems, Springer Verlag, 2017, pp.1-38. ⟨10.1007/s11241-017-9275-6⟩
Real-time systems, 54 (3
Real-Time Systems, Springer Verlag, 2017, pp.1-38. ⟨10.1007/s11241-017-9275-6⟩
Real-time systems, 54 (3
International audience; In this paper, we consider the problem of scheduling hard real-time tasks subjected to preemption delays on a uniprocessor system. While most of the existing work focus on either reducing these additional delays or improving t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a59d0e9e679fb3f9a2adf7ac4e96f7cb
https://hal.archives-ouvertes.fr/hal-01779467
https://hal.archives-ouvertes.fr/hal-01779467
Publikováno v:
Computer Aided Verification ISBN: 9783319633893
CAV (2)
CAV (2)
Static cache analysis characterizes a program’s cache behavior by determining in a sound but approximate manner which memory accesses result in cache hits and which result in cache misses. Such information is valuable in optimizing compilers, worst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::012a384397e3d593d6c64b92b4e509bf
https://doi.org/10.1007/978-3-319-63390-9_2
https://doi.org/10.1007/978-3-319-63390-9_2
Publikováno v:
ACM SIGPLAN Notices
LCTES 2014
ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014
ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014, Jun 2014, Edimbourg, United Kingdom. pp.1-10
HAL
LCTES
LCTES 2014
ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014
ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014, Jun 2014, Edimbourg, United Kingdom. pp.1-10
HAL
LCTES
In systems with hard real-time constraints, it is necessary to compute upper bounds on the worst-case execution time (WCET) of programs; the closer the bound to the real WCET, the better. This is especially the case of synchronous reactive control lo