Zobrazeno 1 - 10
of 135
pro vyhledávání: '"Claire Fenouillet-Beranger"'
Autor:
Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018
https://hal.archives-ouvertes.fr/hal-03434018
Autor:
Anne-Sophie Royet, Claire Fenouillet-Beranger, Laurent Brunet, Pablo Acosta-Alba, Sebastien Kerdiles, Cédric Perrot, F. Aussenac, Jessica Lassarre
Publikováno v:
ECS Transactions. 93:19-22
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8b128c52174d674cc5cc28633710e99
https://doi.org/10.1149/09301.0019ecst
https://doi.org/10.1149/09301.0019ecst
Autor:
Benoit Sklenard, Joris Lacord, D. Lattard, R. Nait Youcef, Xavier Garros, A. Tataridou, Francois Andrieu, Claire Fenouillet-Beranger, F. Balestra, Sylvain Barraud, Perrine Batude, G. Audoit, Mikael Casse, D. Bosch, J. Lugo, Christoforos G. Theodorou, Laurent Brunet, J.-P. Colinge, J. Cluzel, F. Allain, C. Vizioz, J.M. Hartmann
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22aa19246805ca5305905064aa067feb
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
Autor:
F. Balestra, C. Perrot, Joris Lacord, Didier Lattard, Perrine Batude, Benoit Sklenard, V. Benevent, P. Acosta Alba, Sebastien Kerdiles, D. Bosch, Claire Fenouillet-Beranger, J. Lassarre, J. Richy, Francois Andrieu, J.-P. Colinge, Laurent Brunet
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-sili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c9ce1f179d7606adeb1a27fcb299c07c
Autor:
Pablo Acosta-Alba, F. Aussenac, Marc Veillerot, Karim Huet, Hervé Denis, Laurent Brunet, Fulvio Mazzamuto, Bernard Previtali, Perrine Batude, B. Mathieu, Claire Fenouillet-Beranger, I. Toque-Tresonne, Marie-Pierre Samson, Sebastien Kerdiles
Publikováno v:
ECS Transactions. 80:215-225
3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a453e7c7c5b55175c95835d5284a9b6a
https://doi.org/10.1149/08004.0215ecst
https://doi.org/10.1149/08004.0215ecst
Autor:
Claire Fenouillet-Beranger, Maud Vinet, Virginie Beugin, Névine Rochat, Vincent Jousseaume, Perrine Batude, Daniel Benoit, Christophe Licitra, F. Deprat, N. Rambal, G. Imbert, Véronique Caubet-Hilloutou, Chloé Guerin
Publikováno v:
Microelectronic Engineering. 167:90-94
3D sequential integration, such as CoolCubeź, allows to stack vertically layer of devices. Levels of interconnection, also called intermediate Back-End-Of-Line, are needed between successive layers of transistors to avoid routing congestion. Thus, t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8f5a05ab37aeed59e87447a24701c7a
https://doi.org/10.1016/j.mee.2016.11.006
https://doi.org/10.1016/j.mee.2016.11.006
Publikováno v:
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).
Neuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We investigate a novel design to achieve a spiking neuron operator which uses BIMOS transistor combined with a capacitor and a NMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d011ebb3d61b77dddfda6e090f42349e
https://doi.org/10.1109/eurosoi-ulis45800.2019.9041876
https://doi.org/10.1109/eurosoi-ulis45800.2019.9041876
Autor:
Francois Andrieu, L. Ciampolini, G. Cibrario, F. Balestra, Joris Lacord, Xavier Garros, Perrine Batude, Laurent Brunet, A. Makosiej, D. Lattard, Bastien Giraud, Maud Vinet, Claire Fenouillet-Beranger, J.-P. Colinge, Olivier Weber, J. Cluzel, D. Bosch
Publikováno v:
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a29cff3968e6920ebe18ab7cb26addf
https://hal.archives-ouvertes.fr/hal-02998370
https://hal.archives-ouvertes.fr/hal-02998370
Autor:
F. Balestra, A. Makosiej, Joris Lacord, Maud Vinet, Laurent Brunet, E. Esmanhotto, Francois Andrieu, Marco Rios, J. Cluzel, G. Cibrario, Perrine Batude, Olivier Weber, R. Berthelon, D. Lattard, D. Bosch, L. Ciampolini, Claire Fenouillet-Beranger, J.-P. Colinge, Bastien Giraud, S. Lang, Xavier Garros
Publikováno v:
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6339fddbd9f229a6f65ff13fd410189d
https://doi.org/10.1109/vlsi-tsa.2019.8804649
https://doi.org/10.1109/vlsi-tsa.2019.8804649
Autor:
F. Aussenac, P. Acosta-Alba, V. Beugin, V. Mazzocchi, Xavier Garros, Mikael Casse, Sebastien Kerdiles, C. Vizioz, C. Guerin, N. Rambal, F. Ponthenier, J. Micout, Perrine Batude, Maud Vinet, Bernard Previtali, Francois Andrieu, Claire Fenouillet-Beranger, S. Chevalliez, J-M. Pedini, Laurent Brunet
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raise
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2087db0598ab33110cf86534df124584
https://doi.org/10.1109/edtm.2019.8731192
https://doi.org/10.1109/edtm.2019.8731192