Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Ciprian Seiculescu"'
Publikováno v:
2022 IEEE 16th International Symposium on Applied Computational Intelligence and Informatics (SACI).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47108a00d4ee5c2362645bae8f9cf13a
https://doi.org/10.1109/saci55618.2022.9919465
https://doi.org/10.1109/saci55618.2022.9919465
Autor:
Cristina Laura Sirbu, Ciprian Seiculescu, Ghita Adrian Burdan, Tudor Moga, Catalin Daniel Caleanu
Publikováno v:
Australasian Computer Science Week 2022.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2183fe2163bdd40471413945b44c952
https://doi.org/10.1145/3511616.3513111
https://doi.org/10.1145/3511616.3513111
Autor:
Ciprian Seiculescu
Publikováno v:
2021 IEEE 27th International Symposium for Design and Technology in Electronic Packaging (SIITME).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71e6318e22de445ff939cd1d22fba70a
https://doi.org/10.1109/siitme53254.2021.9663723
https://doi.org/10.1109/siitme53254.2021.9663723
Autor:
Elisei Ilies, Magdalena Marinca, Szilard Bularka, Melinda Vajda, Daiana Albulescu, Ciprian Seiculescu
Publikováno v:
2021 IEEE 27th International Symposium for Design and Technology in Electronic Packaging (SIITME).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebcc1230c912296f3d02c984621cb8b0
https://doi.org/10.1109/siitme53254.2021.9663621
https://doi.org/10.1109/siitme53254.2021.9663621
Publikováno v:
Electronics. 11:2545
Deep neural networks have recently become increasingly used for a wide range of applications, (e.g., image and video processing). The demand for edge inference is growing, especially in the areas of relevance to the Internet-of-Things. Low-cost micro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3a4a494b8c75d3d64cf54e3ded87069
https://doi.org/10.3390/electronics11162545
https://doi.org/10.3390/electronics11162545
Autor:
Luca Benini, Giovanni De Micheli, Srinivasan Murali, Hamid Sarbazi-Azad, Dara Rahmati, Ciprian Seiculescu
Publikováno v:
ACM Transactions on Embedded Computing Systems
Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware suppor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::50a5082f79fd634eb4e7b9de07eab870
https://doi.org/10.1145/2485984.2485996
https://doi.org/10.1145/2485984.2485996
Autor:
Pierre-Emmanuel Gaillardon, Vasilis F. Pavlidis, Giovanni De Micheli, Ciprian Seiculescu, Shashikanth Bobba
Publikováno v:
ISCAS
Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e13cbd0776cff8615f7676f9bae337e8
Autor:
Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli, Boris Grot, Ciprian Seiculescu, Stavros Volos
Publikováno v:
Volos, S, Seiculescu, C, Grot, B, Pour, N K, Falsafi, B & De Micheli, G 2012, CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers . in Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on . Institute of Electrical and Electronics Engineers (IEEE), pp. 67-74 . https://doi.org/10.1109/NOCS.2012.15
NOCS
NOCS
Many core chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore's Law. In these architectures, on-chip inter-connects play a pivotal role in ensuring power and performance scalability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f903210b72644cc5aae5a1156b3688b3
https://www.pure.ed.ac.uk/ws/files/18692306/CCNOC_NOCS12.pdf
https://www.pure.ed.ac.uk/ws/files/18692306/CCNOC_NOCS12.pdf
Publikováno v:
CODES+ISSS
Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c694c0313a3f84cc95daeac0e7decfe7
http://hdl.handle.net/11585/132673
http://hdl.handle.net/11585/132673
Publikováno v:
ISVLSI
Most communication traffic in today’s System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM controller. In this paper, we motivate the use of a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5e9848da521f85767f18418611c93421
https://doi.org/10.1109/isvlsi.2011.60
https://doi.org/10.1109/isvlsi.2011.60