Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Churoo Park"'
Autor:
Ho-Jung Kim, Jai-Kwang Shin, Myoung-Jae Lee, Churoo Park, Hongsun Hwang, Chang-Jung Kim, U-In Chung, Hyun-Sik Choi, Sang-beom Kang, Jae-Chul Park, Sanghun Jeon
Publikováno v:
IEEE Transactions on Electron Devices. 58:3820-3828
The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending lim
Autor:
Hong Sun Hwang, Soo Won Kim, Young Hyun Jun, Churoo Park, Byung Sick Moon, Ahn Woo Song, Seong Jin Jang, Jong Pil Son, Joo Sun Choi, Jin-Ho Kim, Seung Uk Han, Satoru Yamada
Publikováno v:
IEICE Transactions on Electronics. :1690-1697
A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system.
Autor:
Kyu-hyoun Kim, Hoe-ju Chung, Yun-Sang Lee, Moo-Sung Chae, Jung-Bae Lee, Soo-In Cho, Jae-Kwan Kim, Dae-Hee Jung, Seung-young Seo, Chang-Hyun Kim, Churoo Park, Jin-hyung Cho, Sung-Ho Choi, Jun-Ho Shin, Ki-whan Song, Taek-Seon Park, Jae-Jun Lee, Seung-Hoon Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:831-838
A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were ach
Autor:
Sung-Yeon Lee, Hyoungsik Nam, Hyun-Jun Yoon, Cheol-Goo Park, Du-Eung Yongin Kim, Jung-Hyeon Lee, Chun-Sup Kim, Beomsup Kim, J.G. Roh, Suyoun Lee, Doo-Sub Lee, Junha Lee, Churoo Park, Sung-Yong Cho, Taesub Jung
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1703-1710
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C. The circuit features are: (1) a bidirectional data strobing sch
Autor:
Yun-Ho Choi, Cheol-soo Kim, Ejaz Haq, Dae-Je Chin, Soo-In Cho, Churoo Park, J. Karp, Seung-Hoon Lee, Si-Yeol Lee, Myung-Ho Kim, Hyun-Soon Jang, Ho-Cheol Lee, Tae-Jin Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:529-533
In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 1
Autor:
Jin Ho Kim, Hongsun Hwang, Seong-Jin Jang, Seung Uk Han, Young-Hyun Jun, Byung-sick Moon, Ahn Woo Song, Joo Sun Choi, Churoo Park, Jong-Pil Son, Soo-Won Kim
Publikováno v:
ESSCIRC
A highly reliable antifuse cell and its sensing scheme that can be actually adopted in DRAM are presented. A multi-cell structure is newly devised to circumvent the large process variation problems of the DRAM cell capacitor type antifuse system. The
Autor:
Sei-Seung Yoon, Seung-Hoon Lee, Il-Jae Cho, Jinman Han, Churoo Park, Domg-Il Seo, Jung-Bae Lee, Se-Jin Jeong
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
A major issue in designing a high speed synchronous DRAM (SDRAM) is how to minimize skews, most of which are generated due lo unequal read/write data paths, different enable/disable times between column select lines (CSLs), unequal distribution of cl
Autor:
Jun-Ho Shin, Dae-Hee Jung, Jae-Kwan Kim, Seung-Hoon Lee, Hoe-ju Chung, Kyu-hyoun Kim, Seung-young Seo, Taek-Seon Park, Sung-Ho Choi, Jae-Jun Lee, Yun-Sang Lee, Jung-Bae Lee, Soo-In Cho, Moo-Sung Chae, Chang-Hyun Kim, Churoo Park, Jin-hyung Cho
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in 80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD protection, rendering C/sub 10/ minimization for the enhanced signal integrity in
Publikováno v:
ICCD
NAND flash memory has become an Indispensable component in embedded systems because of its versatile features such as nonvolatility, solid-state reliability, low cost and high density. Even though NAND flash memory gains popularity as data storage, i
Publikováno v:
1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.
Contact planarization in ULSI multi-level interconnections has been achieved by using a newly developed contact filling technology called Al-PLAPH (Aluminum-Planarization by Post-Heating). In the Al-PLAPH process, Al was initially deposited at room t