Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Chungan Peng"'
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced c
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers a
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4×4 in
Publikováno v:
2008 10th International Conference on Advanced Communication Technology.
This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for decoding the syntax elements such as coeff token, total zero, and run before, but also the decode
Publikováno v:
The 9th International Conference on Advanced Communication Technology.
Discrete cosine transform (DCT), which is an important component of image and video compression, is adopted in various standardized coding schemes, such as JPEG, MPEGx and H.26x. But when compute a two-dimensional (2D) DCT, a large number of multipli
Publikováno v:
MMSP
This paper proposes an efficient and simple architecture for 9/7 Discrete Wavelet Transform based on Distributed Arithmetic. To derive new proposed architecture, we consider the periodicity and symmetry of DWT to optimize the performance and reduce t
Publikováno v:
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several hardware-reduction techniques are investigated and a Sot-SAD-Tree VLSI structure based on SAD-Tree is proposed. Using this Sot-SAD-Tree structure, th
Publikováno v:
2008 9th International Conference on Solid-State & Integrated-Circuit Technology; 2008, p2216-2219, 4p
Autor:
Xiaoxin Cui, Chungan Peng
Publikováno v:
2008 9th International Conference on Solid-State & Integrated-Circuit Technology; 2008, p2208-2211, 4p
Publikováno v:
2008 9th International Conference on Solid-State & Integrated-Circuit Technology; 2008, p1897-1900, 4p