Zobrazeno 1 - 10
of 45
pro vyhledávání: '"Chung-Jin Kim"'
Autor:
Yang-Kyu Choi, Jae-Hyuk Ahn, Hoyeon Kim, Seunghyup Yoo, Jin-Woo Han, Chung-Jin Kim, Sung-Jin Choi
Publikováno v:
ACS Nano. 6:1449-1454
A photoactive memory is implemented on a n-type and p-type double-gate silicon nanowire (Si-NW) field-effect transistor (FET) through the grafting of solution-processable [6,6]-phenyl-C(61)-butyric acid methyl ester (PCBM) in nanogaps. Despite integr
Autor:
Seunghyup Yoo, Hoyeon Kim, Yang-Kyu Choi, Sung-Jin Choi, Jin-Woo Han, Sungho Kim, Chung-Jin Kim
Publikováno v:
Advanced Materials. 23:3326-3331
4–6 ] However, these optoelectronic approaches based on the simple functionalization or the homogeneous integration of organic channel/organic-based gate dielectrics still show intrinsic problems in memory functionality, such as unstable hysteresis
Autor:
Yang-Kyu Choi, Chung Jin Kim, Seong Wan Ryu, Hyun Gyu Park, Jin-Woo Han, Changhoon Kim, Cheulhee Jung
Publikováno v:
Biosensors and Bioelectronics. 25:2182-2185
Gold nanoparticle (GN) embedded silicon nanowire (SiNW) configuration was proposed as a new biosensor for label-free DNA detection to enhance the sensitivity. The electric current flow between two terminals, a source and a drain electrode, were measu
Publikováno v:
IEEE Transactions on Electron Devices. 56:3228-3231
A novel initialization concept is demonstrated to improve the program efficiency of the 1T-DRAM mode of unified random access memory (URAM). The proposed method involves boosting the gate-induced drain leakage current for the generation of excess hol
Publikováno v:
IEEE Transactions on Electron Devices. 56:3232-3235
The isolation-dielectric effects of a FinFET structure with a partially depleted (PD) silicon-on-insulator (PDSOI) region as a charge storage node on the characteristics of 1T-DRAM are reported in this brief. By introducing the low-permittivity isola
Autor:
Jin-Woo Han, Gi-Sung Lee, Jae-Sub Oh, Yang-Kyu Choi, Jeoung Woo Kim, Seong-Wan Ryu, Jin Soo Kim, Chung-Jin Kim, Kwang Hee Kim, Sung-Jin Choi, Sungho Kim, Meyong-Ho Song, Yun Chang Park
Publikováno v:
IEEE Transactions on Electron Devices. 56:601-608
This paper investigates how gate height (Hg), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a
Autor:
Jae-Hyuk Ahn, Gi-Sung Lee, Chung-Jin Kim, Dong-Hyun Kim, Jae-Sub Oh, Kwang Hee Kim, Seong-Wan Ryu, Kyu Jin Choi, Yang-Kyu Choi, Yun Chang Park, Byung Jin Cho, Jin-Woo Han, Sung-Jin Choi, Myeong-Ho Song, Jeoung Woo Kim, Sungho Kim, Jin-Soo Kim
Publikováno v:
IEEE Transactions on Electron Devices. 56:641-647
A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si1-yCy substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in
Publikováno v:
IEEE Transactions on Electron Devices. 55:1472-1479
A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poisson's equation is obtained with the approximation that a vertical channel potential distribution is a cubic function
Autor:
Jee-Yeon Kim, Gi-Sung Lee, Yang-Kyu Choi, Jae-Sub Oh, Chung-Jin Kim, Dong-Il Moon, Jin-Woo Han, Jin-Seong Lee, Yun-Chang Park, Dongwook Lee, Young-Su Kim, Sung-Jin Choi, Dae-Won Hong, Jeoung-Woo Kim
Publikováno v:
IEEE Electron Device Letters. 32:452-454
A gate length of 25 nm and a silicon nanowire (SiNW) with a width of 6 nm and a height of 10 nm fully surrounded by a gate are demonstrated. A suspended SiNW, which is fully depleted, is fabricated on a bulk substrate by employing the deep reactive-i
Autor:
Sung-Jin Choi, Seong-Wan Ryu, Yang-Kyu Choi, Dong-Il Moon, Jin-Woo Han, Chung-Jin Kim, Dong-Hyun Kim, Sungho Kim
Publikováno v:
IEEE Electron Device Letters. 30:742-744
A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess hol