Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Chung-Hao Fu"'
Autor:
Hang-Ting Lue, Chung-Hao Fu, Tzu-Hsuan Hsu, Ming-Liang Wei, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu
Publikováno v:
2022 IEEE Silicon Nanoelectronics Workshop (SNW).
A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances
Autor:
Chung-Hao Fu, Chih-Yuan Lu, Keh-Chung Wang, Wei-Chen Chen, Guan-Ru Lee, Hang-Ting Lue, Chia-Jung Chiu, Tzu-Hsuan Hsu
Publikováno v:
IEEE Transactions on Electron Devices. 67:989-994
A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping
Autor:
Kuei-Shu Chang-Liao, Li-Jung Liu, Chen-Chien Li, Tzu-Hsiang Su, Wei-Fong Chi, Chia-Chi Tsai, Mong-Chi Li, Yu-Wei Chang, Chung-Hao Fu, Chun-Chang Lu, Ting-Chun Chen
Publikováno v:
IEEE Electron Device Letters. 37:12-15
Electrical characteristics of Ge pMOSFETs with HfO2, ZrO2, ZrO2/HfO2, and HfZrO x gate dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in ZrO2 device, which, however, has a higher interface trap density (
Autor:
Chun-Chang Lu, Tsung-Lin Hsieh, Yan-Lin Li, Li-Ting Chen, Chung-Hao Fu, Dun-Bao Ruan, Yu-Liang Liao, Chen-Chien Li, Kuei-Shu Chang-Liao
Publikováno v:
Microelectronic Engineering. 138:81-85
Display Omitted A post-growth treatment is performed on interfacial layer before high-k deposition.The treatment includes an IL desorption and a re-growth process.Both effective oxide thickness and simultaneously leakage current are decreased.The imp
Autor:
Mong-Chi Li, Tien-Ko Wang, Chen-Chien Li, Zong-Hao Ye, Li-Ting Chen, Hao-Zhi Hong, Chun-Chang Lu, Chung-Hao Fu, Kuei-Shu Chang-Liao, Wei-Fong Chi
Publikováno v:
Solid-State Electronics. 101:33-37
High-k gated metal–oxide–semiconductor field-effect-transistors (MOSFETs) with Cl 2 and CF 4 plasma treatments are studied in this work. A higher-k HfON with more tetragonal phase is formed by the halogen plasma treatment on interfacial layer (IL
Autor:
Chun-Chang Lu, Jen-Wei Cheng, Chen-Chien Li, Li-Jung Liu, Chung-Hao Fu, Kuei-Shu Chang-Liao, Ting-Ching Chen
Publikováno v:
IEEE Transactions on Electron Devices. 61:2662-2667
A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm 2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO 2 with a higher k value (k ~ 31) and co
Autor:
Li-Ting Chen, Tsung-Lin Hsieh, Chen-Chien Li, Yu-Liang Liao, Chun-Chang Lu, Chung-Hao Fu, Tien-Ko Wang, Kuei-Shu Chang-Liao
Publikováno v:
Microelectronic Engineering. 109:64-67
Display Omitted We study the high-k dielectrics with in situ NH3, N2, H2 plasma treatment.EOT and Jg are reduced for the MOS device with NH3 plasma treated HfO2.A tetragonal phase HfO2 is obtained for the MOS device with NH3 plasma treatment.Stress i
Autor:
Ting-Ching Chen, Chen-Chien Li, Chun-Chang Lu, Hao-Zhi Hong, Chi-Fong Ai, Tien-Ko Wang, Kuei-Shu Chang-Liao, Te-Hsuen Tzeng, Wen-Fa Tsai, Chung-Hao Fu
Publikováno v:
Solid-State Electronics. 78:17-21
Metal oxide semiconductor field effect transistors (MOSFET) with SiGe channel and higher-k gate dielectric are studied in this work. Samples with TaON/HfO2 or TiON/HfO2 stacks show larger drain current, better transconductance, and smaller subthresho
Autor:
Chung-Hao Fu, Wei-Hao Tseng, Chun-Chang Lu, Kuei-Shu Chang-Liao, Yu-Chen Li, Tien-Ko Wang, Chi-Fong Ai, Wen-Fa Tsai
Publikováno v:
Microelectronic Engineering. 88:1560-1563
MOSFET devices with Ge channel and nitridation treatment using plasma immersion ion implantation (PIII) are studied in this work. Experimental results show that the electrical characteristics and reliability of Ge MOSFETs can be significantly improve
Autor:
Chi-Fong Ai, Chun-Chang Lu, Kuei-Shu Chang-Liao, Ya-Yin Hsu, Tien-Ko Wang, Fu-Chung Hou, Yao-Tung Hsu, Yan-Lin Li, Che-Hao Tsao, Chung-Hao Fu, Wen-Fa Tsai, Yu-An Chang, Dawei Heh
Publikováno v:
ECS Transactions. 35:39-53
The effects of interfacial layer at high-k dielectric/Si substrate formed by using stress-relieved pre-oxide (SRPO) treatment on electrical characteristics of MOS devices were studied in this work. The equivalent oxide thickness value could be scaled