Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Chun-Cheng Tsao"'
Autor:
Chun-cheng Tsao, 曹淳誠
103
This paper aims to explore a rhetorical perspective of televised financial News, which is a narrative. And Chosen “quantitative easing” (QE) report from a famous TV program “Sisy’s FINANCE WEEKLY” as a case study. By using narrativ
This paper aims to explore a rhetorical perspective of televised financial News, which is a narrative. And Chosen “quantitative easing” (QE) report from a famous TV program “Sisy’s FINANCE WEEKLY” as a case study. By using narrativ
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/he735w
Publikováno v:
International Symposium for Testing and Failure Analysis.
Convention hand polishing, which is widely used for delayering, is becoming increasingly difficult as metal lines and stacks in semiconductor devices get thinner. For one thing, endpointing at the exact targeted layer and region of interest is a majo
Autor:
Hideo Tanaka, Chun-Cheng Tsao
Publikováno v:
Microelectronics Reliability. 114:113935
Circuit Edit (CE) techniques have been used for debug, characterization and prototyping. in the IC industry. CE jobs have become more complex to accomplish since the adaption of FinFET technology. Backside Si trenching as part of CE process is requir
Publikováno v:
2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
In this study we demonstrate the use of phase shift of lock-in thermography (LIT) a powerful technique in characterizing the Z profile of 2.5D packages. It is interesting to have a good understanding of how a given package structure correlates with L
Publikováno v:
International Symposium for Testing and Failure Analysis.
This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware invo
Publikováno v:
Microelectronics Reliability. 42:1667-1672
Publikováno v:
Microelectronics Reliability. 41:1545-1549
Publikováno v:
Microelectronics Reliability. 39:957-961
We have developed a new, fully integrated circuit timing analysis tool that provides measurements of electrical waveforms by direct access to the diffusion nodes through the backside of CMOS integrated circuits. The system, known as the IDS 2000, all
Autor:
Mitchio Okumura, Chun-Cheng Tsao, Julio D. Lobo, Seth Blumberg, Theodore S. Dibble, Xu Zhang, Shui-Yin Lo
Publikováno v:
Journal of Applied Physics. 81:5896-5904
Time-of-flight measurements were made of neutral helium atom beams extracted from a repetitive, pulsed, positive-point corona discharge. Two strong neutral peaks, one fast and one slow, were observed, accompanied by a prompt photon peak and a fast io
Publikováno v:
International Symposium for Testing and Failure Analysis.
Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LV