Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Chun C. Lee"'
Autor:
Amy Whitcombe, Chun C. Lee, Asma Beevi Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent Carlton, Peter Sagazio, Stefano Pellerano, Christopher Hull
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:972-982
Autor:
Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher Hull, Stefano Pellerano
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:3582-3598
Autor:
Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios Dogiamis, Brent Carlton, Mark Chakravorti, Stefano Pellerano, Christopher Hull
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Michael P. Flynn, Chun C. Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:859-869
Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but h
Publikováno v:
VLSIC
A 12b 70MS/s sub-2 radix SAR ADC designed on Intel's 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn't require accurate references
Publikováno v:
International Journal of High Speed Electronics and Systems. 15:255-275
This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch
Autor:
Chun C. Lee, Michael P. Flynn
Publikováno v:
2010 Symposium on VLSI Circuits.
A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b stage resolution. A “half-gain” MDAC reduces the output
Autor:
Michael P. Flynn, Chun C. Lee
Publikováno v:
2008 IEEE Symposium on VLSI Circuits.
A 14 b 23 MS/s ADC that pipelines a 2nd order resetting SigmaDelta modulator with a 10 b cyclic ADC and requires no front-end S/H is presented. The architecture uses a resetting SigmaDelta modulator at the front-end for accuracy and a cyclic ADC at t
Publikováno v:
Nuclear and Chemical Waste Management. 7:37-41
A mobile plasma arc system for the destruction of liquid hazardous wastes has been designed and constructed. The pyrolytic destruction process produces acid gas, a fuel gas, and finely divided carbon. The acid gas is removed in a caustic scrubber, wh
Publikováno v:
Archiv f�r Mikrobiologie. 88:205-212
The marine blue-green alga, Trichodesmium, was collected from the Gulf Stream, near Miami, and occurred in two distinct colonial forms both of which reduced acetylene to ethylene. Trichodesmium was more abundant during the summer but its acetylene-re