Zobrazeno 1 - 10
of 35
pro vyhledávání: '"Chuei-Tang Wang"'
Autor:
Douglas C. H. Yu, Chuei-Tang Wang, Chia-Chia Lin, Chih-Hsin Lu, Gene Wu, Chien-Yuan Huang, Wei-Ting Chen, Terry Ku, Kuo-Chung Yee, Chung-Hao Tsai
Publikováno v:
IEEE Transactions on Electron Devices. 69:7167-7172
Autor:
Chuei-Tang Wang, Chia-Chai Lin, Chih-Hsin Lu, Wei-Ting Chen, Chung-Hao Tsai, Douglas C. H. Yu
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Autor:
Terry Ku, Tsung-Shu Lin, Jeng-Shien Hsieh, Chun Shu-Rong, Douglas Yu, Hao-Yi Tsai, Chung-Shi Liu, Tin-Hao Kuo, Chuei-Tang Wang
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A novel wafer-scale system integration solution, InFO_SoW (System-on-Wafer), has been successfully developed to integrate known-good chips arrays with power and thermal module for high performance computing. InFO_SoW eliminates the use of substrate a
Autor:
Wu Kai-Chiang, Chung-Hao Tsai, Tang Tzu-Chun, Doug C. H. Yu, Chung-Shi Liu, Che-Wei Hsu, Chuei-Tang Wang, Pu Han-Ping, Chia-Chia Lin, Lu Chun-Lin
Publikováno v:
2019 Electrical Design of Advanced Packaging and Systems (EDAPS).
High Q-factor (quality factor) 3D solenoid inductor formed by RDL (redistribution layer) and copper via in the molding compound on InFO package was fabricated. The effect of the turns and cross sectional area on Q-factor is discussed. The 3D solenoid
Autor:
Chuei-Tang Wang, Douglas Yu
Publikováno v:
3DIC
Novel InFO technologies have been developed to meet high bandwidth, low power consumption and small form factor requirements for system integration with key characteristics of thin dielectric layers, fine RDL lines, 3D vertical interconnects and mult
Autor:
Victor C. Y. Chang, Shih-Ya Huang, Chuei-Tang Wang, H. P. Pu, Jeng-Shien Hsieh, Douglas Yu, T. Ko
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level
Autor:
H. P. Pu, Chun-Wen Lin, Chung-Hao Tsai, Chuei-Tang Wang, Che-Wei Hsu, Jeng-Shien Hsieh, Tzu-Chun Tang, Douglas Yu, Wu Kai-Chiang
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
InFO_AiP technology, with low loss chip-to-antenna interconnect and wideband slot-coupled patch antenna, is proposed for low power, high performance, and compact 5G millimeter wave (mmWave) system integration. The low loss chip-to-antenna interconnec
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GH
Autor:
Chuei-Tang Wang, Douglas Yu
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can p