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Publikováno v:
2006 IEEE International Conference on Semiconductor Electronics.
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::652f0c6cfd07fb2662eb7812471edda6
https://doi.org/10.1109/smelec.2006.381114
https://doi.org/10.1109/smelec.2006.381114
