Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Christos Vezyrtzis"'
Autor:
Michael J. Klaiber, George D. Gristede, Shih-Hsien Lo, Hiroshi Inoue, Leland Chang, Christos Vezyrtzis, Jungwook Choi, Gary W. Maier, Fanchieh Yee, Shubham Jain, Brian W. Curran, Jintao Zhang, Mingu Kang, Howard M. Haynie, Mauricio J. Serrano, Pong-Fei Lu, Silvia Melitta Mueller, Matthew M. Ziegler, Bruce M. Fleischer, Kazuaki Ishizaki, Kailash Gopalakrishnan, Michael R. Scheuermann, Ankur Agarwal, Xiao Sun, Sunil Shukla, Thomas W. Fox, Vijayalakshmi Srinivasan, Tina Babinsky, Swagath Venkataramani, Michael A. Guillorn, Ching Zhou, Nianzheng Cao, Eri Ogawa, Naigang Wang, Moriyoshi Ohara, Joel Abraham Silberman, Jinwook Oh, Marcel Schaal, Chia-Yu Chen, Wei Wang
Publikováno v:
Proceedings of the IEEE. 108:2232-2250
Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered the explosive growth of AI workloads across the spectrum of computing devices. However, th
Autor:
Matthew M. Ziegler, Sunil Shukla, Gary W. Maier, Jinwook Oh, Kailash Gopalakrishnan, Christos Vezyrtzis, Thomas W. Fox, Michael J. Klaiber, Howard M. Haynie, Swagath Venkataramani, Leland Chang, Jungwook Choi, Nianzheng Cao, Pong-Fei Lu, Pierce Chuang, Michael A. Guillorn, Brian W. Curran, Dongsoo Lee, Fanchieh Yee, Ankur Agrawal, Ching Zhou, Silvia Melitta Mueller, Naigang Wang, George D. Gristede, Bruce M. Fleischer, Michael R. Scheuermann, Tina Babinsky, Vijayalakshmi Srinivasan, Chia-Yu Chen, Joel Abraham Silberman, Shih-Hsien Lo
Publikováno v:
IEEE Solid-State Circuits Letters. 1:217-220
This letter presents a multi-TOPS AI accelerator core for deep learning training and inference. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range of neural network topologies by employin
Autor:
Maria Kurchuk, Bob Schell, Sharvil Patil, Yannis Tsividis, Steven M. Nowick, Christos Vezyrtzis, Pablo Martinez-Nuevo
Publikováno v:
Event-Based Control and Signal Processing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e04d77e0630a30b5aca12f9b25bf365
https://doi.org/10.1201/b19013-15
https://doi.org/10.1201/b19013-15
Autor:
Jungwook Choi, Ching Zhou, Naigang Wang, Ankur Agrawal, Michael J. Klaiber, Matthew M. Ziegler, Fanchieh Yee, Shih-Hsien Lo, Sunil Shukla, George D. Gristede, Bruce M. Fleischer, Michael R. Scheuermann, Chia-Yu Chen, Michael A. Guillorn, Kailash Gopalakrishnan, Joel Abraham Silberman, Jinwook Oh, Howard M. Haynie, Thomas W. Fox, Vijayalakshmi Srinivasan, Brian W. Curran, Gary W. Maier, Swagath Venkataramani, Nianzheng Cao, Pong-Fei Lu, Christos Vezyrtzis, Tina Babinsky, Silvia Melitta Mueller, Pierce Chuang, Leland Chang, Dongsoo Lee
Publikováno v:
ISLPED
The combination of growth in compute capabilities and availability of large datasets has led to a re-birth of deep learning. Deep Neural Networks (DNNs) have become state-of-the-art in a variety of machine learning tasks spanning domains across visio
Autor:
Shih-Hsien Lo, Brian W. Curran, Jinwook Oh, Howard M. Haynie, Vijavalakshmi Srinivasan, Lel Chang, Fanchieh Yee, Tina Babinsky, Joel Abraham Silberman, George D. Gristede, Matthew M. Ziegler, Gary W. Maier, Bruce M. Fleischer, Michael R. Scheuermann, Nianzheng Cao, Ankur Agrawal, Ching Zhou, Chia-Yu Chen, Silvia Melitta Mueller, Jungwook Choi, Naigang Wang, Kailash Gopalakrishnan, Thomas W. Fox, Sunil Shukla, Swagath Venkataramani, Michael J. Klaiber, Christos Vezyrtzis, Pierce Chuang, Dongsoo Lee, Michael A. Guillorn, Pong-Fei Lu
Publikováno v:
VLSI Circuits
A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range
Autor:
David T. Hui, Pierce I-Jen Chuang, Eickhoff Susan M, Alper Buyuktosunoglu, Phillip J. Restle, Michael Stephen Floyd, Richard F. Rizzolo, Preetham M. Lobo, S. Carey, Tobias Webel, Christos Vezyrtzis, Ramon Bertran, Gerard M. Salem, Thomas Strach, Pawel Owczarczyk, Stelios G. Tsapepas
Publikováno v:
ISSCC
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating,
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2009-2022
A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, t
Autor:
Martin Cochet, John-David Wellman, Ramon Bertran, Christos Vezyrtzis, Arun Paidimarri, Mircea R. Stan, Augusto Vega, Hans M. Jacobson, Subhasish Mitra, Rajiv V. Joshi, Swagath Venkataramani, Karthik Swaminathan, Daniel Friedman, David Brooks, Pradip Bose, Matthew M. Ziegler, Jeff Burns, Schuyler Eldridge, Alper Buyuktosunoglu, Robert K. Montoye, Eric Cheng, Nandhini Chandramoorthy, Gu-Yeon Wei, Kevin Skadron, Pritish R. Parida
Publikováno v:
ICCD
This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the pe
Autor:
Kevin Skadron, Alper Buyuktosunoglu, Klas Lilja, Keith Campbell, Hyungmin Cho, Deming Chen, Mircea R. Stan, Lukasz G. Szafaryn, Binh Quang Le, Shahrzad Mirkhani, Pradip Bose, Eric Cheng, Subhasish Mitra, Cheng-Yong Cher, Jacob A. Abraham, Christos Vezyrtzis
Publikováno v:
ICCD
CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (ene
Autor:
Michael Stephen Floyd, Alper Buyuktosunoglu, Phillip J. Restle, Richard F. Rizzolo, Gerard M. Salem, Preetham M. Lobo, Thomas Strach, Divya Pathak, Pierce I-Jen Chuang, S. Carey, Otto Torreiter, Christos Vezyrtzis, Malcolm Scott Ware, Ramon Bertran, Tobias Webel
Publikováno v:
ISSCC
Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module