Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Christos P. Sotiriou"'
Autor:
Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno
Publikováno v:
IEEE Access, Vol 9, Pp 54286-54297 (2021)
Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use h
Externí odkaz:
https://doaj.org/article/db168a37c1c041648add24fffb055994
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:1063-1074
Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and propos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::adf5785ca052515500008dbb01b59bc9
https://doi.org/10.1109/tvlsi.2006.884148
https://doi.org/10.1109/tvlsi.2006.884148
Publikováno v:
Microprocessors and Microsystems. 28:561-571
Summarization: Network data are, currently, often encrypted at a low level. In addition, as it is widely supported, the majority of future networks will use low-layer (IP level) encryption. Moreover, current trends imply that future networks are like
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f2fa2a3edeb8b71e8bc2647fc17d17b6
https://doi.org/10.1016/j.micpro.2004.08.009
https://doi.org/10.1016/j.micpro.2004.08.009
Publikováno v:
VLSI Design
Asynchronous circuits, despite demonstrated advantages for certain application areas, remain outside of mainstream digital design practices. Existing asynchronous synthesis flows for concurrent specifications either exhibit NP complexity, e.g. incur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc69b82c160048908a9bd6ed395fe03e
https://doi.org/10.1109/vlsid.2013.196
https://doi.org/10.1109/vlsid.2013.196
Publikováno v:
ICCD
FSM and PTnet control models are pertinent in both software and hardware applications as both specification and implementation models. The state-based, monolithic FSM model is directly implementable in software or hardware, but cannot model concurren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::161af6e47661b7f97504fd16d4954ec1
https://doi.org/10.1109/iccd.2012.6378645
https://doi.org/10.1109/iccd.2012.6378645
Publikováno v:
DAC
Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate- level circuit into
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9383336935ac99ce36d8def00bf980aa
https://doi.org/10.1109/dac.2007.375308
https://doi.org/10.1109/dac.2007.375308
Publikováno v:
FPL
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. Actual-delay circuits operate according to the actual, physical device
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c1d7dcca51879346e2608cb28c965f8
https://doi.org/10.1109/fpl.2006.311272
https://doi.org/10.1109/fpl.2006.311272
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2d2d2f3a3417b2835f15210f2827c8be
Autor:
V. Zebilis, Christos P. Sotiriou
Publikováno v:
ASYNC
Prior research in event spacing has identified two effects which contribute to the phenomenon of bursting events in self-timed systems, namely the Charlie and the Drafting effects. In this paper, we attempt to further the understanding of these effec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d967b4b0bd1978f20b2f29c78bad024a
https://doi.org/10.1109/async.2005.16
https://doi.org/10.1109/async.2005.16
Publikováno v:
ASYNC
Locally generated, arbitrated clocks for GALS SoCs as stated in S. Moore et al. (April 2002) face the risk of synchronization failures if clock delays are not accounted for. The problem is analyzed based on clock delays, cycle times, and complexity o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24af49e3c57aee5afb984882089e6660
https://doi.org/10.1109/async.2004.1299298
https://doi.org/10.1109/async.2004.1299298