Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Christopher V. Baiocco"'
Autor:
Arifuzzaman (Arif) Sheikh, J. Chen, Michael V. Aquilino, Mukesh Khare, James Chingwei Li, Weipeng Li, X. Chen, Laegu Kang, G. Massey, J. Sudijono, An L. Steegen, Vijay Narayanan, Jin-Ping Han, M. Zaleski, Rashmi Jha, Haoren Zhuang, M. Chowdhury, C. Reddy, Douglas D. Coolbaugh, Yi-Wei Lee, Michael P. Chudzik, Kenneth J. Stein, Zhenrong Jin, Shesh Mani Pandey, D. Tekleab, S. Samavedam, Christopher V. Baiocco, Haining Yang, Deleep R. Nair, JiYeon Ku, Chandrasekharan Kothandaraman, Craig S. Lage, Jaeger Daniel, R. Mo, C. Hobbs, S. Kalpat, Da Zhang, Naim Moumen, Nam-Sung Kim, S. Kirshnan, J. Wallner, X. Wang, R. Lindsay, Melanie J. Sherony, Aaron Thean, Young Way Teh
For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ad4bb3545ca27a0a35b2cac57515af2c
https://doi.org/10.1109/vlsit.2008.4588573
https://doi.org/10.1109/vlsit.2008.4588573
Autor:
J. Pape, Nam-Sung Kim, Martin Ostermayr, Deleep R. Nair, Melanie J. Sherony, Craig S. Lage, Jaeger Daniel, Franck Arnaud, Y. Gao, Deok-Hyung Lee, H.S. Yang, C. Schiller, X. Chen, S. Stiffler, An L. Steegen, Kenneth J. Stein, J. Sudijono, Christopher V. Baiocco, Haoren Zhuang, Robert C. Wong, Y. Takasu, Ho-Kyu Kang, Sayeed A. Badrudduza, J. Wallner, Laegu Kang, James Chingwei Li, Aaron Thean, Y.W. Teh, L. Zhuang, R. Hasumi, S. Samavedam, D.P. Sun, Mukesh Khare
Publikováno v:
2008 IEEE International Electron Devices Meeting.
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcc347a597544ead57bce41996b65ef0
https://doi.org/10.1109/iedm.2008.4796660
https://doi.org/10.1109/iedm.2008.4796660
Autor:
I. Yang, F. Zhang, A. Tilke, P. Wrschka, Y.-H. Lin, J. Lian, P. Nguyen, V. Ramanchandran, Gregory M. Johnson, L.S. Leong, Atul C. Ajmera, A. Ebert, S.O. Kim, H. Zhuang, M.-C. Sun, J.-P. Kim, Andy Cowley, Christopher V. Baiocco, J.-H. Ku, W. Lin, J. Greg Massey, Alvin G. Thomas, M. Naujok, A. Vayshenker, G. Leake, A. Fischer, M. Sherony, E. Kaltalioglu, K. Hooper, Dirk Vietzke, C. Griffin, Y.-W. Teh, W. Gao, J. Sudijohno, Manfred Eller, Randy W. Mann, G. Matusiewicz, Y.K. Siew, T. Schiml, Renee T. Mo, S.-M. Choi, R. Knoefler, W.L. Tan, J. Benedict, T. Pompl, J.-H. Yang, F.F. Jamin, Fernando Guarin, K.C. Park, K.-W. Lee, An L. Steegen, Jae-Eun Park, S. Scheer, V. Klee, D.H. Hong, L. Tai, V. Ku, S.L. Liew
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80b515e6807384d732a1a136ebc7ef9d
https://doi.org/10.1109/iedm.2005.1609267
https://doi.org/10.1109/iedm.2005.1609267
Autor:
Erdem Kaltalioglu, Zhijiong Luo, Victor Ku, Y. H. Lin, A. Ajmera, Seong-Dong Kim, T. Schiml, W. L. Tan, S. Marokkey, P. Wrschka, Dirk Vietzke, M. Weybright, F.F. Jamin, R. Mo, D.-G. Park, An L. Steegen, Wenhe Lin, Padraic Shafer, Terence B. Hook, V. Klee, JiYeon Ku, Rajesh Rengarajan, C. Wann, K. Kim, Jenny Lian, Andy Cowley, Victor Chan, Sunfei Fang, A. Vayshenker, K-C. Lee, Christopher V. Baiocco, I. Yang, L. Kim, Manfred Eller, Randy W. Mann, B. Zhang, C. Coppock, Mark Hoinkis, J. Sudijono, Huilong Zhu, Phung T. Nguyen
Publikováno v:
Scopus-Elsevier
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d5455847fc85f7a2c23cdb1895e40c02
https://doi.org/10.1109/iedm.2004.1419254
https://doi.org/10.1109/iedm.2004.1419254
Autor:
Victor Chan, See-Hun Yang, E.J. Nowak, Padraic Shafer, Shih-Fen Huang, Ashima B. Chakravarti, An L. Steegen, Wei Jin, Terence B. Hook, Nivo Rovedo, Phung T. Nguyen, D. Lea, Jia Chen, Rajesh Rengarajan, C. Wann, X. Chen, Christopher V. Baiocco, Hung Ng, Victor Ku
Publikováno v:
Scopus-Elsevier
A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d0a1dfd2b2688d2350c7f6b60ead98b1
https://doi.org/10.1109/iedm.2003.1269170
https://doi.org/10.1109/iedm.2003.1269170