Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Christopher J. Bostak"'
Autor:
Nevine Nassif, Jason Crop, Brian Brock, Christopher J. Bostak, Jayen J. Desai, Dave Bradley, Arvind Raghavan, C. Houghton, Daniel W. Krueger, Olivier Franza, C. Morganti, Bill Bowhill, Sal Bhimji, B. Stackhouse, Mendoza Oscar, Zibing Yang, Matthew Becker
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:92-104
The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4–2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e24b3135ebe4be2d20a49543de8b8287
https://doi.org/10.1109/jssc.2015.2472598
https://doi.org/10.1109/jssc.2015.2472598
Autor:
P. Gronowski, B. Cherkauer, Daniel W. Krueger, B. Stackhouse, C. Morganti, M.K. Gowan, Dave Bradley, E. Francom, S. Troyer, Christopher J. Bostak, Jayen J. Desai, Sal Bhimji
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:18-31
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e462ba22f3dd3e25996f2e4277d45c7
https://doi.org/10.1109/jssc.2008.2007150
https://doi.org/10.1109/jssc.2008.2007150
Autor:
Arvind Raghavan, Dave Bradley, Zibing Yang, C. Houghton, Matthew Becker, B. Stackhouse, Daniel W. Krueger, Olivier Franza, Bill Bowhill, Sal Bhimji, Nevine Nassif, C. Morganti, Christopher J. Bostak, Jason Crop, Jayen J. Desai
Publikováno v:
ISSCC
The next-generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64b Haswell cores [1], 45MB L3 cache, 4 DDR4-2133MHz memory channels, 40 8GT/s PCIe lanes, and 60 9.6GT/S QPI lanes. The processor has 5.56B transist
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b50772a373a14368c865919a2c7896d
https://doi.org/10.1109/isscc.2015.7062934
https://doi.org/10.1109/isscc.2015.7062934
Autor:
Christopher J. Bostak, W.H. Parks, M. Millican, C. Poirier, R. McGowen, James S. Ignowski, S. Naffziger
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:229-237
This paper describes the embedded feedback and control system on a 90-nm Itanium family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbee05bb6fdbf68f16f7599b26d68701
https://doi.org/10.1109/jssc.2005.859902
https://doi.org/10.1109/jssc.2005.859902
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
This paper describes the embedded feedback and control system on a 90 nm Itanium/spl reg/-family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system utilizes on-ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1d130caaac9d6ce9588503763e3da26
https://doi.org/10.1109/isscc.2005.1493990
https://doi.org/10.1109/isscc.2005.1493990
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