Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Christopher D. Muzzy"'
Autor:
Tunga Krishna R, R. Mendelson, I. Melville, J. Coffin, E. Misra, C. Carey, Thomas A. Wassick, David Questad, Christopher D. Muzzy
Publikováno v:
International Symposium on Microelectronics. 2015:000787-000792
The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include
Autor:
Mark C. H. Lamorey, Timothy H. Daubenspeck, R. Bisson, Thomas A. Wassick, K. Smith, Hosadurga Shobha, Dimitri R. Kioussis, Griselda Bonilla, J. Wright, S. Tetreault, David B. Stone, I. Paquin, Timothy M. Shaw, E. Misra, Gordon C. Osborne, Brian R. Sundlof, X.-H. Liu, Christopher D. Muzzy, S. S. Bouchard, David L. Questad
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
This study examines different approaches to determining the chip failure rate that occurs due to dielectric cracking under C4 sites during chip joining. We show that testing of the strength of individual C4s by a single bump shear technique gives a s
Autor:
Timothy H. Daubenspeck, Timothy M. Shaw, X.-H. Liu, Christopher D. Muzzy, Griselda Bonilla, S. S. Bouchard, Thomas A. Wassick, David B. Stone, David L. Questad, Brian R. Sundlof, Hosadurga Shobha, Dimitri R. Kioussis, I. Paquin, E. Misra, Gordon C. Osborne, J. Wright, S. Tetreault, R. Bisson, Mark C. H. Lamorey
Publikováno v:
2015 IEEE International Integrated Reliability Workshop (IIRW).
The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibilit
Autor:
E. Kinser, Eric Turcotte, Robert Hannon, Julien Sylvestre, Christopher D. Muzzy, H. Gagnon, J.-G. Quintal, G. Mongeau, David Danovitch, P.V. McLaughlin, J. Wright
Publikováno v:
2008 58th Electronic Components and Technology Conference.
An evaluation of 65 nm and 45 nm CMOS technology in a stacked die package is presented. The technology uses SiCOH advanced low K and ultra low K back end of line (BEOL) for high performance. A BEOL specific test vehicle was fabricated in these techno
Autor:
Conal E. Murray, Ian D. Melville, Matthew Angyal, Xiao Hu Liu, Jennifer V. Muncy, Vincent J. McGahay, Henry A. Nye, Charles F. Carey, Mukta G. Farooq, M. Cullinan-Scholl, Robert Hannon, Michael Lane, David L. Questad, T. Shaw, Wolfgang Sauter, Christopher D. Muzzy, P.V. McLaughlin
Publikováno v:
2007 IEEE International Interconnect Technology Conferencee.
This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4
Autor:
John A. Fitzsimmons, Vincent J. McGahay, K. Malone, M. Minami, Siddhartha Panda, Manfred Horstmann, A. Wei, Helmut Bierstedt, H. Nii, A. Waite, A. Sakamoto, Michael A. Gribelyuk, M. Cullinan-Scholl, D. Harmon, A. Hellmich, M. Kiene, Patrick Press, Hartmut Ruelke, H. Zhu, H. Chen, H. Nakayama, Anthony G. Domenicucci, G. Sudo, Henry A. Nye, P. Fisher, Hans-Jürgen Engelmann, H. VanMeer, M. Newport, X. Chen, Tenko Yamashita, Cathryn Christiansen, Hasan M. Nayfeh, Dureseti Chidambarrao, Guido Koerner, Christopher D. Muzzy, S.-F. Huang, Ralf Otterbach, David M. Fried, J. Kluth, Jörg Hohage, M. Trentsch, I. Peidous, Thorsten Kammler, Mukesh Khare, Dominic J. Schepis, K. Rim, Spooner Terry A, K. Miyamoto, P.V. McLaughlin, Michael Raab, T. H. Ivers, Dan Mocuta, D.R. Davies, Jason Gill, Scott Luning, Woo-Hyeong Lee, Gary B. Bronner, Judson R. Holt, Gregory G. Freeman, Matthias Schaller, R. Murphy, J. Pellerin, J. Klais, Kai Frohberg, A. Neu, N. Kepler, R. Bolam, C. Labelle, Anuj Madan, K. Hempel, C. Reichel, Heike Salz, J. Hontschel, T. Sato, J. Cheng, D. Greenlaw, Linda Black, Paul D. Agnello, K. Ida
Publikováno v:
Scopus-Elsevier
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a n
Autor:
T. Iijima, Nicholas C. M. Fuller, Satya V. Nitta, Vincent J. McGahay, Qinghuang Lin, Shom Ponoth, Jason Gill, C. Labelle, S. H. Chen, Derren N. Dunn, Spooner Terry A, Stephan A. Cohen, C. Tyberg, James R. Lloyd, Henry A. Nye, Christopher D. Muzzy
Publikováno v:
2006 International Interconnect Technology Conference.
We have demonstrated porous ultra low-K (ULK)/Cu interconnect integration using via first integration scheme and a direct ULK CMP process. The key features of the damage-resistant porous ULK material were novel material chemistry, a higher carbon con
Autor:
J.C. Patel, Johnny Widodo, Anita Madan, Robert L. Wisnieff, Darryl D. Restaino, Brian Wayne Herbst, Spooner Terry A, Jason Gill, Hosadurga Shobha, C. Labelle, Stephan A. Cohen, Michael Lane, Eva E. Simonyi, Kelly Malone, X.-H. Liu, Y. Shimooka, Christopher D. Muzzy, Griselda Bonilla, P. Minami, Alfred Grill, John A. Fitzsimmons, T. H. Ivers, Steven E. Molis, Eric G. Liniger, Son Nguyen, Vincent J. McGahay, Robert Hannon, Henry A. Nye, T. Lee, Brett H. Engel, M. Kiene, F. Chen, Stephan Grunow, Cathryn Christiansen, M. Cullinan-Scholl, Derren N. Dunn, Timothy M. Shaw, Habib Hichri, Jeremy L. Martin, N. Klymko, P.V. McLaughlin, K. Ida, James J. Demarest, A. Sakamoto
Publikováno v:
2006 International Interconnect Technology Conference.
A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and proces
Autor:
E. Duchesne, T. Ivers, C.-C. Yang, Clare Johanna Mccarthy, D. Hawken, Charles R. Davis, Timothy H. Daubenspeck, M. Cullinan, Larry Clevenger, J. Wright, T. Aoki, James J. Demarest, C. Das, Jon A. Casey, T. Shaw, Michael Lane, Daniel C. Edelstein, J. Nadeau-Filteau, Thomas E. Lombardi, A. Cowley, William F. Landers, David L. Questad, F. Beaulieu, X.-H. Liu, Wolfgang Sauter, Christopher D. Muzzy, Luc Guerin
Publikováno v:
Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator
Autor:
W.-K. Li, Chester T. Dziobkowski, Stephan A. Cohen, Michael Lane, K. Ida, C.-C. Yang, Jeremy L. Martin, S. Vogt, T. Van Kleeck, Jason Gill, David L. Questad, Philip L. Flaitz, William F. Landers, X.-H. Liu, Christopher D. Muzzy, T. Ivers, T. Shaw, Kaushik Chanda, J. Wright, M. Cullinan, Takeshi Nogami, A. Sakamoto, Son Nguyen, Larry Clevenger, W. Cote, M. Yoon, A. Cowley, S. Tempest, Charles R. Davis, Daniel C. Edelstein, David P. Klaus, James J. Demarest, Andrew H. Simon, Swastika N. Das, Anita Madan, C. Parks, Stephen M. Gates, W. Wille, Darryl D. Restaino, John A. Fitzsimmons, S. Molis, Du Binh Nguyen, R. G. Filippi, Birendra N. Agarwala, D. Hawken, S. Arai, M. Ono, N. Klymko, Y.-H. Lin, A. Carbone, Joe Lee, Hazara S. Rathore, Derren N. Dunn, Alfred Grill, Eric G. Liniger, S. Lane, Y. Shimooka, Yanfeng Wang, Sandra G. Malhotra, Timothy J. Dalton, P. Davis, E. Simonyi
Publikováno v:
Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k.