Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Christophe Regnier"'
Autor:
Francois Leverd, Christophe Regnier, J. Bustos, B. Tavel, Thomas Skotnicki, Francois Wacquant, S. Harrison, Philippe Coronel, A. Beverina
Publikováno v:
Microelectronic Engineering. 72:321-325
We report on a new concept for realization of transistors with high-k oxide by deposition through the contact holes. This new integration allows low thermal budget for the high-k film (deposited after source and drain anneal), no particular contamina
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b35cd6ee77a21820fda615da8e09934
https://doi.org/10.1016/j.mee.2004.01.030
https://doi.org/10.1016/j.mee.2004.01.030
Autor:
K. Bard, S. Van, Francois Wacquant, H. Achard, P. Spinelli, M. Muller, Roland Pantel, D. Rabilloud, R. Palla, Pierre Morin, V. Tirard, O. Leborgne, Christophe Regnier, E. Olson, D. Ceccarelli, V. DeJonghe, Tushar Mandrekar, V. Carron, B. Froment, V. Gravey, H. Brut, F. Trentesaux, A. Halimaoui, S. Lis, J. Diedrick, Frederic Boeuf, A. Beverina
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b3a4635456f0e378db88788bfd36555
https://doi.org/10.1109/essderc.2003.1256852
https://doi.org/10.1109/essderc.2003.1256852
Autor:
P.O. Sassoulas, Francois Wacquant, J. Todeschini, M. Woo, M. Charpin, Y. Laplanche, N. Revil, J.C. Oberlin, Roland Pantel, B. Hinschberger, O. Belmont, D. Neira, P. Stolk, Franck Arnaud, M. Broekaart, Frederic Boeuf, I. Guilmeau, D. Ceccarelli, Francois Leverd, N. Emonet, Damien Lenoble, Bertrand Borot, G. Imbert, N. Bicais, S. Delmedico, A. Sicard, Nicolas Planes, J. Farkas, Christophe Regnier, V. Vachellerie, J. Uginet, Chittoor Parthasarathy, E. Denis, V. DeJonghe, Pierre Morin, T. Devoivre, H. Brut, R. Palla, Laurent Pain, P. Vannier, F. Salvetti, A. Beverina, C. Perrot
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f57f1b2bcd5199626774a2f09c78af07
https://doi.org/10.1109/vlsit.2003.1221088
https://doi.org/10.1109/vlsit.2003.1221088