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Publikováno v:
CICC
A 5th order continuous time delta sigma modulator is designed in 0.18μm CMOS. At a sampling rate of 500MHz it achieves 76dB SNDR over a 10MHz bandwidth consuming 58mW. 5th order noiseshaping is realized with 4 opamp based RC integrators and a VCO re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8700617c2404654d658f5ed27702f3c9
https://doi.org/10.1109/cicc.2013.6658527
https://doi.org/10.1109/cicc.2013.6658527
