Výsledky vyhledávání - "Choong-keun Kwak"

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

Publikováno v: IEEE Journal of Solid-State Circuits. 43:150-162

A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3bb56c06a68aad78d573d48f4282847e
https://doi.org/10.1109/jssc.2007.908001

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A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Publikováno v: IEEE Journal of Solid-State Circuits. 42:210-218

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5ac21a148dba58b8028a73848294492b
https://doi.org/10.1109/jssc.2006.888349

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Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory

Autor: Sang-beom Kang, Du-Eung Kim, Byung-Gil Choi, Gitae Jeong, Beak-Hyung Cho, Kinam Kim, Hyung-Rok Oh, Hyun-Geun Byun, Woo Yeong Cho, Hye-Jin Kim, Ki-Sung Kim, Choong-keun Kwak, Hongsik Jeong

Publikováno v: IEEE Journal of Solid-State Circuits. 41:122-126

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::94cfb2e131b410ec79036049fd050880
https://doi.org/10.1109/jssc.2005.859016

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Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM

Autor: Seungjin Lee, Chang-Hyun Kim, Woo-Yeong Cho, Hoi-Jun Yoo, Jerald Yoo, Chang-Sik Kim, Choong-keun Kwak, Byung-Gil Choi, Kyomin Sohn, Hyejung Kim, Bo-Tak Lim, Jeong-Ho Woo

Publikováno v: 2007 IEEE Symposium on VLSI Circuits.

A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled b

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cfb82d768f9989b510c66cc66fe809c2
https://doi.org/10.1109/vlsic.2007.4342707

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A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

Publikováno v: ISSCC

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f65c7e0083e2afc1b5695f454bb9522b
https://doi.org/10.1109/isscc.2007.373499

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A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

Publikováno v: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 256Mb PRAM featuring synchronous burst read operation is developed. Using a charge-pump system, write performance is characterized at 1.8V supply. Measured initial read access time and burst-read access time are 62ns and 10ns, respectively. The max

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::044a5b4e8beaa5c0453a939083bd2098
https://doi.org/10.1109/isscc.2006.1696081

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64Mb mobile stacked single-crystal Si SRAM (S/sup 3/RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM

Autor: Bo-Tak Lim, Jong-Pil Son, Hung-Jun An, Kyung-Hee Kim, Hyun-Sun Mo, Gong-Heum Han, Hyou-Youn Nam, Joon-Min Park, Hyun-Geun Byun, Su-Yeon Kim, Choong-keun Kwak, Sang-beom Kang

Publikováno v: 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 64Mb Mobile S/sup 3/RAM was designed with stacked single-crystal thin film transistor (SSTFT) cell using 80nm SRAM technology to overcome chip size penalty of conventional 6T-SRAM with improved performance. For 1.3V operation, word line (WL) and ce

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::353872c04ef2d361058036c963f3cd94
https://doi.org/10.1109/vlsic.2004.1346588

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A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

Autor: Sang-beom Kang, Hyung-Rok Oh, Young-Nam Hwang, Beak-Hyung Cho, Ki-Sung Kim, Suseob Ahn, Du-Eung Kim, Hongsik Jeong, Byung-Gil Choi, Kyung-Hee Kim, Hyun-Geun Byun, Gwan-Hyeob Koh, Choong-keun Kwak, Kinam Kim, Gitae Jeong, Woo Yeong Cho

Publikováno v: 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 51

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c16883055e0beed93e7af538aa6d6d78
https://doi.org/10.1109/isscc.2004.1332583

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