Zobrazeno 1 - 10
of 57
pro vyhledávání: '"Cho W. Moon"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14:45-60
We propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. We first establish a relation between STG's and finite state machines (FSM's). Then we solve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::626253d58da27a992880e9cd2aa25e7e
https://doi.org/10.1109/43.363124
https://doi.org/10.1109/43.363124
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 7:85-100
This article describes three aspects of asynchronous design from a Petri-net specification called asignal transition graph (STG). First, we show that the STG defined by Chu [1] is too restrictive for specifying general asynchronous behavior and propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e0d83074632d61debf151a7957951da
https://doi.org/10.1007/bf02108191
https://doi.org/10.1007/bf02108191
Autor:
Robert K. Brayton, K.J. Singh, Alberto Sangiovanni-Vincentelli, Hamid Savoj, E.M. Sentovich, Cho W. Moon
Publikováno v:
ICCD
A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88c2117e2cad03ab495039a290008367
https://doi.org/10.1109/iccd.1992.276282
https://doi.org/10.1109/iccd.1992.276282
Publikováno v:
ICCAD
The authors propose some syntactic and semantic extensions to a graphical specification called the signal transition graph (STG). They allow controlled-choice places to have fanout transitions of input signals and arbitrary Boolean expressions can be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd60ebf55942a6cc8266dc432f405479
https://doi.org/10.1109/iccad.1991.185265
https://doi.org/10.1109/iccad.1991.185265
Publikováno v:
DAC
A timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from a gate-level netlist by reducing a timing graph. Previous methods
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdf2263ab07cafefcc3660a2cb2891e0
https://doi.org/10.1145/513918.513957
https://doi.org/10.1145/513918.513957
Publikováno v:
Asynchronous Circuit Design for VLSI Signal Processing ISBN: 9781461362081
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7a08d2f6bc2b3b630806a93a9fc0e03
https://doi.org/10.1007/978-1-4615-2794-7_7
https://doi.org/10.1007/978-1-4615-2794-7_7
Autor:
Cho W. Moon, Robert K. Brayton
Publikováno v:
DAC
We propose a novel method to eliminate dynamic hazards in asynchronous circuits synthesized from the signal transition graph (STG) specifications. We first review a relationship between syntactic constraints such as liveness and complete state coding
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c9823c9aace9f7873355e109e3691e0
https://doi.org/10.1145/157485.164551
https://doi.org/10.1145/157485.164551
Autor:
Betti, Gianni, Evangelista, Daniela, Gagliardi, Francesca, Giordano, Emanuele, Riccaboni, Angelo
Publikováno v:
Sustainability (2071-1050); Aug2024, Vol. 16 Issue 15, p6330, 26p
Autor:
Jang, Haeyoung, Kwon, Seung-Ho
Publikováno v:
Economic & Labour Relations Review (Cambridge University Press); Jun2022, Vol. 33 Issue 2, p351-376, 26p