Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Chiung-San Lee"'
Autor:
Tai-Ming Parng, Chiung-San Lee
Publikováno v:
Journal of Parallel and Distributed Computing. 38:16-27
This paper presents a performance model of a two-dimensional disk array (TIDA) system, which is composed of several major subsystems including disk cache, intelligent disk array controller, SCSI-like I/O bus, and two-dimensional array of disk devices
Autor:
Tai-Ming Parng, Chiung-San Lee
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 7:755-767
A methodology, called Subsystem Access Time (SAT) modeling, is proposed for the performance modeling and analysis of shared-bus multiprocessors. The methodology is subsystem-oriented because it is based on a Subsystem Access Time Per Instruction (SAT
Publikováno v:
Journal of the Chinese Institute of Engineers. 18:553-563
This paper presents a performance model of a special shared bus multiprocessor system, that features: (1) separate address‐bus and data‐bus with split transaction, pipelined cycle; (2) two‐level cache structure; and (3) multiple main memory and
Publikováno v:
Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference. 2007
Electronic medical record exchanges can save time and reduce cost by eliminating redundant data and typing errors. The major steps of record exchange consist of querying information from database, encoding data into messages, and sending and decoding
Publikováno v:
SPDP
The paper presents an analytical model of a whole disk array architecture, XDAC, which consists of several major subsystems and features: the two-dimensional array structure; IO-bus with split transaction protocol; and cache for processing multiple I
Publikováno v:
ICPADS
This paper presents the performance modelling and evaluation of a shared bus multiprocessor, XMP. A key characteristic of XMP is that it employs a special shared bus scheme featuring separate address bus and data bus with split transaction, pipelined
Autor:
Hung-Pin Chen, Chiung-San Lee
Publikováno v:
SMC
This paper presents the design of a High Speed Multistage Fuzzy Hardware (HSMFH) architecture for fuzzy logic control. In multistage fuzzy rules, there are input, intermediate, and output variables. The intermediate variable is found in the then-part
Publikováno v:
2007 29th Annual International Conference of the IEEE Engineering in Medicine & Biology Society; 2007, p3657-3660, 4p
Publikováno v:
Proceedings of 1994 6th IEEE Symposium on Parallel & Distributed Processing; 1994, p620-627, 8p
Publikováno v:
Proceedings of 1994 International Conference on Parallel & Distributed Systems; 1994, p446-453, 8p