Zobrazeno 1 - 10
of 41
pro vyhledávání: '"Chiu Pi-Feng"'
In cloud and edge computing models, it is important that compute devices at the edge be as power efficient as possible. Long short-term memory (LSTM) neural networks have been widely used for natural language processing, time series prediction and ma
Externí odkaz:
http://arxiv.org/abs/2002.10636
Autor:
Tung Thanh Hoang, Wen Ma, Martin Lueker-Boden, Chiu Pi-Feng, Won Ho Choi, Zvonimir Z. Bandic, Gertjan Hemink
Publikováno v:
ISCAS
An SLC NAND array based in-flash computing core is proposed for enabling vector-matrix multiplications in binarized neural network (BNN) and binary weight network (BWN). Two SLC NAND floating gate (FG) cells in the same string store complementary dat
Autor:
Rick Galbraith, Daniel Bedau, Dirk J. Wouters, T. Hennen, J. A. J. Rupp, Chiu Pi-Feng, Won Ho Choi, Rainer Waser, Jonas A. Goode, Martin Lueker-Boden, Wen Ma
Publikováno v:
ISCAS
In this work, we use a Cr-doped V2O3 based Mott oscillator circuit to build a reservoir computing system that has much smaller model size than an equivalent LSTM. In contrast to an LSTM, our reservoir computing system can be trained very efficiently
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
ICRC
In cloud and edge computing models, it is important that compute devices at the edge be as power efficient as possible. Long short-term memory (LSTM) neural networks have been widely used for natural language processing, time series prediction and ma
Publikováno v:
ISCAS
Binarized Neural Networks (BNN) significantly reduce computational complexity and relax memory requirements with binarized weights and activations. We propose a differential crosspoint (DX) memristor array for enabling parallel multiply-and-accumulat
Publikováno v:
ICMLA
The noise effect during training and inference for deep artificial neural network hardware acceleration is analyzed in this paper. The noise effect is extremely important when designing hardware for machine learning due to non-ideal devices and circu
Autor:
Celio, Christopher1 (AUTHOR), Chiu, Pi-Feng1 (AUTHOR), Asanovic, Krste1 (AUTHOR), Nikolic, Borivoje1 (AUTHOR), Patterson, David1 (AUTHOR)
Publikováno v:
IEEE Micro. Mar/Apr2019, Vol. 39 Issue 2, p52-60. 9p.
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency techniques are needed to tolerate process-induced defects, variation, and aging in SRAM cells. Many different resiliency schemes have been proposed an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1b5e1c0b4d0bf0917835bfda1dc67a2b
https://kluedo.ub.uni-kl.de/frontdoor/index/index/docId/4314
https://kluedo.ub.uni-kl.de/frontdoor/index/index/docId/4314
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.