Zobrazeno 1 - 10
of 41
pro vyhledávání: '"Chittoor Parthasarathy"'
Autor:
Anuj Grover, David Turgis, Ivan Miro-Panades, Shamsi Azmi, Bastien Giraud, Guillaume Moritz, G. S. Visweswaran, Chittoor Parthasarathy, Jean-Philippe Noel, Mohammad Daud, Promod Kumar, Edith Beigne, Philippe Flatresse
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:2438-2447
An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35–1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential sup
Publikováno v:
2019 41st Annual EOS/ESD Symposium (EOS/ESD).
This work analyzes the TLP and (vf)-TLP characteristics of NMOS driver design in FDSOI technology. A TCAD model based on electro-thermal simulations is developed, that captures the measured characteristics in single NMOS drivers in ON/OFF state condi
Autor:
David Meyer, Abhishek Jain, S. Mhira, Chittoor Parthasarathy, Vincent Huard, Florian Cacho, S. Naudet, Alain Bravaix, A. Benhassain
Publikováno v:
ITC
2017 IEEE International Test Conference (ITC)
2017 IEEE International Test Conference (ITC), Oct 2017, Fort Worth, France. pp.1-7, ⟨10.1109/TEST.2017.8242042⟩
2017 IEEE International Test Conference (ITC)
2017 IEEE International Test Conference (ITC), Oct 2017, Fort Worth, France. pp.1-7, ⟨10.1109/TEST.2017.8242042⟩
International audience; This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised mach
Autor:
Chittoor Parthasarathy, S. Naudet, Alain Bravaix, Abhishek Jain, Florian Cacho, Vincent Huard, S. Mhira, A. Benhassain
Publikováno v:
Psicologia: Teoria e Pesquisa
Psicologia: Teoria e Pesquisa, 2017, IEEE International Symposium on
Testing and Robust System Design (IOLTS), ⟨10.1109/IOLTS.2017.8046204⟩
IOLTS
Psicologia: Teoria e Pesquisa, 2017, IEEE International Symposium on
Testing and Robust System Design (IOLTS), ⟨10.1109/IOLTS.2017.8046204⟩
IOLTS
International audience; New insights on the stochastic nature of aging-related timing impact in digital circuits trigger the need for aging compensation control loop. Such control loops enable additional 22% power savings but require dedicated safety
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1b21e6f242882112236f5658ad0cb898
https://hal.science/hal-03654374
https://hal.science/hal-03654374
Autor:
Frederic Robert, Jean-Claude Marin, Radhika Gupta, Chittoor Parthasarathy, Shafquat Jahan Ahmed, Yagnesh Dineshbhai Vaderiya
Publikováno v:
SPIE Proceedings.
In advanced technology nodes, layout regularity has become a mandatory prerequisite to create robust designs less sensitive to variations in manufacturing process in order to improve yield and minimizing electrical variability. In this paper we descr
Autor:
Chittoor Parthasarathy, Abhishek Jain, S. Mhira, A. Benhassain, Vincent Huard, S. Naudet, Alain Bravaix, Florian Cacho
Publikováno v:
2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2017, Unknown, Unknown Region
2017 IEEE International Reliability Physics Symposium (IRPS)
2017 IEEE International Reliability Physics Symposium (IRPS), Apr 2017, Monterey, France. pp.3A-4.1-3A-4.7, ⟨10.1109/IRPS.2017.7936279⟩
2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2017, Unknown, Unknown Region
2017 IEEE International Reliability Physics Symposium (IRPS)
2017 IEEE International Reliability Physics Symposium (IRPS), Apr 2017, Monterey, France. pp.3A-4.1-3A-4.7, ⟨10.1109/IRPS.2017.7936279⟩
IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, APR 02-06, 2017; International audience; A novel control loop enables Dynamic Adaptive Voltage Scaling in a demonstrator with digital cores tightly coupled with monitors and Dynam
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b0473b6bc0c0d11c3dbc4fcd9af71def
https://hal.archives-ouvertes.fr/hal-01694458
https://hal.archives-ouvertes.fr/hal-01694458
Autor:
A. Benhassain, Florian Cacho, Chittoor Parthasarathy, Abhishek Jain, V. Knopik, S. Mhira, P. Cathelin, Lorena Anghel, Ajith Sivadasan, Vincent Huard
Publikováno v:
IOLTS
Reliability for advanced CMOS nodes is becoming very challenging. The trade-off between high performance and reliability requirement can no longer be addressed by rough extra-margin. It would results in an overdesign and strong penalty of performance
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
This work provides elements to highlight the fundamental elements towards an Aging-aware Adaptive Voltage Scaling (A-AVS) scheme of digital circuits. Through main milestones including monitors' definition and insertion flow, monitors' characterizatio
Autor:
David Meyer, Abhishek Jain, Chittoor Parthasarathy, S. Naudet, Vincent Huard, Alain Bravaix, S. Mhira, Florian Cacho
Publikováno v:
2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016, Unknown, Unknown Region
2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016, Unknown, Unknown Region
IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, APR 17-21, 2016; International audience; This work demonstrates the fundamental aspects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1867d57b38d2233a581c4b7275fba55e
https://hal.archives-ouvertes.fr/hal-01435230
https://hal.archives-ouvertes.fr/hal-01435230
Publikováno v:
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability, 2007, IEEE Transactions on Device and Materials Reliability, 7 (4), pp.558-570. ⟨10.1109/TDMR.2007.911380⟩
IEEE Transactions on Device and Materials Reliability, 2007, IEEE Transactions on Device and Materials Reliability, 7 (4), pp.558-570. ⟨10.1109/TDMR.2007.911380⟩
International audience; A practical and accurate Design-in-Reliability methodology has been developed for designs on 90–65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Si