Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Chiou-Feng Chen"'
Autor:
Caleb Yu-Sheng Cho, Prateep Tuntasood, Tseng-Yi Liu, Ming-Jer Chen, Chiou-Feng Chen, Der-Tsyr Fan
Publikováno v:
IEEE Transactions on Electron Devices. 53:465-473
A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d39261214e938732a5eb5b0954cf979
https://doi.org/10.1109/ted.2005.863764
https://doi.org/10.1109/ted.2005.863764
Publikováno v:
IEEE Electron Device Letters. 23:422-424
Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I/sub D/=I/sub 0/ exp[q(V/sub GB/ - nV/sub SB/)/nkT], a mathematical fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cd639bd9888bec91d3bd9abde420130
https://doi.org/10.1109/led.2002.1015226
https://doi.org/10.1109/led.2002.1015226
Autor:
Ching-Yuan Wu, Chiou-Feng Chen
Publikováno v:
Solid-State Electronics. 35:705-716
A physical model has been developed to analyze the dynamic characteristics of a FLOTOX EEPROM device. The effects of the structural parameters such as the area and thickness of the tunneling-oxide and interpoly-oxide layers are characterized by a cou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34cdac38f1d36b7e38726de53f38e163
https://doi.org/10.1016/0038-1101(92)90041-a
https://doi.org/10.1016/0038-1101(92)90041-a
Autor:
J.Y. Pan, Caleb Yu-Sheng Cho, Jung-Chang Lu, A. Hsu, Chi-Wei Hung, H.H. Kuo, Da Sung, C.L. Chen, Vincent Huang, P. Tuntasood, Der-Tsyr Fan, I.C. Chuang, Chi-Shan Wu, Cheng-Yuan Hsu, B. Sheen, C.C. Hsue, K. Tseng, S.C. Chen, Chiou-Feng Chen
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accompli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::114d362957e69dd2b13b8c0b142ab45b
https://doi.org/10.1109/vlsit.2004.1345403
https://doi.org/10.1109/vlsit.2004.1345403
Publikováno v:
International Conference on Microelectronic Test Structures, 2003..
A fast and precise subthreshold slope method for extraction of gate capacitive coupling coefficient is substantially confirmed by experimental data from three types of flash memory cells: stacked gate, sidewall source-side injection (SSI), and split-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8985fa49887acf9951eaae7e2302e1e5
https://doi.org/10.1109/icmts.2003.1197459
https://doi.org/10.1109/icmts.2003.1197459
Publikováno v:
International Conference on Microelectronic Test Structures, 2003; 2003, p186-190, 5p
Autor:
Ching-Yuan Wu, Chiou-Feng Chen
Publikováno v:
IEEE Transactions on Electron Devices; 1987, Vol. 34 Issue 7, p1590-1602, 13p
Publikováno v:
IEEE Transactions on Electron Devices; 1987, Vol. 34 Issue 7, p1540-1552, 13p
Autor:
Chiou‐Feng Chen, Ching‐Yuan Wu
Publikováno v:
Journal of Applied Physics. 60:3926-3944
The constant‐current‐stressed voltage‐time (V‐t) characteristics of the thin SiO2 films thermally grown on the silicon substrate has been analyzed by using a theoretical model which includes the effects of dynamic trapping (i.e., electron tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::214d55582d257093991a64b487309ac1
https://doi.org/10.1063/1.337515
https://doi.org/10.1063/1.337515
Autor:
Ching-Yuan Wu, Chiou-Feng Chen
Publikováno v:
Solid-State Electronics. 29:1059-1068
A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics and impact ionization has been developed to characterize the ramp-voltage stressed current-voltage characteristics of thin o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e5f04dc8987bab4a9cd99ae757ed2cf
https://doi.org/10.1016/0038-1101(86)90106-1
https://doi.org/10.1016/0038-1101(86)90106-1