Zobrazeno 1 - 10
of 95
pro vyhledávání: '"Chingwei Yeh"'
Autor:
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
Publikováno v:
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::274e6063c788001e69aade037e0bb4cd
https://doi.org/10.1109/asp-dac52403.2022.9712584
https://doi.org/10.1109/asp-dac52403.2022.9712584
Publikováno v:
2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA).
This paper presents the life period estimation of stamping process by analyzing its punch sounds with a deep neural network (DNN). Neuro-approximated MFCC (NA-MFCC) feature extraction has also been proposed to trade estimation accuracy for computatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10c8043110edb0f5510cd2e92c95b7c0
https://doi.org/10.1109/iciea.2019.8833634
https://doi.org/10.1109/iciea.2019.8833634
Publikováno v:
NGCAS
This paper presents the algorithm and architecture for approximate distribute arithmetic (ADA), which tolerates timing faults in SRAM- or ROM-based lookup tables (LUT) at ultra-low voltages by applying fine-grained bit-slice skipping and compensation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30c179d43a096030ac7496d8fcbb4654
https://doi.org/10.1109/ngcas.2017.39
https://doi.org/10.1109/ngcas.2017.39
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:597-601
During systems-on-a-chip (SoC) integration, silicon intellectual properties (IPs) are generally regarded as blockages to long interconnections that connect different IPs. With this constraint, conventional designs are forced to place those repeaters
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e16ee23106af978c3553d41b2319b062
https://doi.org/10.1109/tvlsi.2012.2190434
https://doi.org/10.1109/tvlsi.2012.2190434
Publikováno v:
GCCE
Overdrive technique is mandatory for liquid crystal display (LCD) to mitigate the motion blur phenomenon. As the display resolution increases, the image data should be highly compressed to reduce the usages of frame memory and bandwidth. Since curren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f30b36512002c434f6bf96fd7214958f
https://doi.org/10.1109/gcce.2016.7800313
https://doi.org/10.1109/gcce.2016.7800313
Publikováno v:
SoCC
Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2× code s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a23e2d45acc814154658f1bc958f34d8
https://doi.org/10.1109/socc.2016.7905495
https://doi.org/10.1109/socc.2016.7905495
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1929-1937
This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, sever
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4fc07b7af632034317add67b5f1f83b
https://doi.org/10.1109/tvlsi.2011.2169435
https://doi.org/10.1109/tvlsi.2011.2169435
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 8:1-27
Power gating is an effective technique for reducing leakage power in deep submicron CMOS technology. Microarchitectural techniques for power gating of functional units have been developed by detecting suitable idle regions and turning them off to red
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::004b88f941103b4d55c50498d78b2a69
https://doi.org/10.1145/2019608.2019615
https://doi.org/10.1145/2019608.2019615
Publikováno v:
IEICE Transactions on Electronics. :913-916
CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cau
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4aafc1028f395ab04bad5d785dda44d5
https://doi.org/10.1587/transele.e94.c.913
https://doi.org/10.1587/transele.e94.c.913
Publikováno v:
Journal of Circuits, Systems and Computers. 19:1817-1834
Deep pipeline has traditionally been widely used in high performance microprocessor. To allow continuous program execution, branch prediction provides a necessary method of speculatively executing instructions without compromising performance. Howeve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c341203da41217a7a5018acfd2fdb328
https://doi.org/10.1142/s0218126610007146
https://doi.org/10.1142/s0218126610007146