Zobrazeno 1 - 10
of 485
pro vyhledávání: '"Ching-Te Chuang"'
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 4, Iss 2, Pp 76-82 (2016)
This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixedmode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits pr
Externí odkaz:
https://doaj.org/article/0669081a3f414a9ab237717585cae220
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 5, Iss 2, Pp 101-115 (2015)
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations includi
Externí odkaz:
https://doaj.org/article/9c5c3044a4a149f2a745d1ee16c2331c
Autor:
Ching-Te Chuang, Chien-Yu Lu
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 2, Iss 4, Pp 282-300 (2012)
This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped
Externí odkaz:
https://doaj.org/article/bde5051298ad452fb2bb0cd99490258f
Autor:
Wei-Sheng Peng, Kuen-Di Lee, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Ming-Hsien Tu, Ching-Te Chuang, Huan-Shun Huang, Kuang-Yu Li, Yung-Shin Kao, Wei Hwang
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:1791-1802
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::860ca831f5c59066616d86125b97cbea
https://doi.org/10.1109/tcsi.2017.2681738
https://doi.org/10.1109/tcsi.2017.2681738
Publikováno v:
IEEE Transactions on Electron Devices. 64:2445-2451
For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc9814e63d82b6f573c3eba5b9b53ea8
https://doi.org/10.1109/ted.2017.2685561
https://doi.org/10.1109/ted.2017.2685561
Autor:
Jr-Ming Chen, Jeng Ren Duann, Yan-Huei You, Ching-Te Chuang, Yu-Chieh Huang, Tzai-Wen Chiu, Wei Hwang, Jin-Chern Chiou, Yan-Yu Huang, Yen-Han Lin, Yu-Tao Yang, Shang-Lin Wu, Po-Tsang Huang, Yu-Chen Hu, Kuan-Neng Chen, Hsiao-Chun Chang
Publikováno v:
IEEE Transactions on Electron Devices. 64:1666-1673
In the traditional neural sensing microstructure, the limited metal line pitch and the metal layer numbers restrict the neural signal routing ability from electrodes to circuit chips. Miniature packaging and excessive noise interference bottlenecks a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a97a7a9e973bae78ced0132052220390
https://doi.org/10.1109/ted.2017.2660763
https://doi.org/10.1109/ted.2017.2660763
Autor:
Huan-Jan Tseng, Ching-Te Chuang, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei Hwang, Wei-Chang Wang
Publikováno v:
SoCC
For energy-constrained multi-sensing IoT devices, ultra-low-power queueing is one of the critical event-driven design challenges to capture low-speed sensing data with various sampling frequencies. In this paper, 0.3V 1W2R sub-threshold FIFO memory i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7cce272ac99e6f067125c907ed23efb0
https://doi.org/10.1109/socc46988.2019.1570555748
https://doi.org/10.1109/socc46988.2019.1570555748
Publikováno v:
IEEE Electron Device Letters. 37:928-931
This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e093ce933cc6bc992d21da892c53acba
https://doi.org/10.1109/led.2016.2564998
https://doi.org/10.1109/led.2016.2564998
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
Autor:
Ming Hsien Tu, Shang-Lin Wu, Yung Shin Kao, Ching-Te Chuang, Huan Shun Huang, Kuen Di Lee, Chien-Yu Lu
Publikováno v:
Microelectronics Journal. 51:89-98
This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fac3f497ce2ad9b66f910ad82667d7e
https://doi.org/10.1016/j.mejo.2016.02.011
https://doi.org/10.1016/j.mejo.2016.02.011
Publikováno v:
IEEE Transactions on Electron Devices. 63:625-630
For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electros
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d37d0e92a74bd9911cde678f23180474
https://doi.org/10.1109/ted.2015.2505064
https://doi.org/10.1109/ted.2015.2505064