Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Ching-Ji Huang"'
Publikováno v:
VLSI-DAT
This paper presents an energy-scalable computing platform for flexible and smart WSN edge applications. The platform comprises a 32-bit OpenRISC processor and two 4KB instruction and data caches on a chip, which can be operated in a wide supply volta
Autor:
Kuo-Chiang Chang, Yuan-Hua Chu, Liang-Chia Cheng, Shien-Chun Luo, Ming-Pin Chen, Po-Hsun Chen, Ching-Ji Huang, Chih-Wei Liu, Yi-Fang Chiu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:947-951
This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:1656-1665
Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restri
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 60:677-681
Pulse-triggered flip-flops are candidates to improve pipeline speed, although flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Pulse-triggered flip-flops usually have specific structures and transisto
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 56:1160-1172
Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are d
Publikováno v:
ISCAS
This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path f
Publikováno v:
2007 IEEE International Behavioral Modeling and Simulation Workshop.
Hierarchical statistical analysis using the regression-based approach is often used to improve the extremely expensive HSPICE Monte Carlo (MC) analysis. However, accurately fitting the regression equations requires many simulation samples. In this pa
Publikováno v:
ISCAS
System-on-a-chip with multiple power domains reduces leakage power consumption by power gating which shut off the idle blocks. Power gating is an effective technology to reduce sub-threshold leakage current. However, without good understanding and ca