Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chin-Ming Fu"'
Autor:
Chao-Chieh Li, Sheng-Yao Yang, Sandeep Kumar Goel, Shu-Chun Yang, Tze-Chiang Huang, Kenny Hsieh, Chien-Chun Tsai, King-Ho Tam, Wen-Hung Huang, Ching-Fang Chen, Stefan Rusu, Yu-Chi Chen, Frank Lee, Mei Wong, Chi-Wei Hu, Chin-Ming Fu, Mu-Shan Lin
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:956-966
We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A7
A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications
Publikováno v:
VLSI Circuits
This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line based "TRIG-after-SAMP" approach relaxes timing margins and eliminates high-speed clock sour
Autor:
Alvin Leng Sun Loke, Chien-Chun Tsai, C. H. Kenny, Tsung-Hsien Tsai, Wen-Hung Huang, Yu-Chi Chen, Chin-Hua Wen, Wei Chih Chen, Chin-Ming Fu
Publikováno v:
VLSI Circuits
We present a high-accuracy wideband quadrature clock generator (QCG) built in 5nm finFET CMOS. To achieve low power and high bandwidth, we employ an active poly phase filter (APPF) to generate the quadrature phases with 6dB gain boost and 30% bandwid
Autor:
Jack Hu, Mei Wong, Tom Chen, Chien-Chun Tsai, Wen-Hung Huang, Mu-Shan Lin, Sandeep Kumar Goel, Chin-Ming Fu, Chao-Chieh Li, Shu-Chun Yang, Stefan Rusu, Frank Lee, Cheng-Hsiang Hsieh, Sheng-Yao Yang, Tze-Chiang Huang, King-Ho Tam, Yu-Chi Chen
Publikováno v:
VLSI Circuits
A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet
Autor:
Chin, Ming-Fu, 秦銘甫
106
For the past few years, offline retailers have started to develop warehousing and logistics management further by information technology. Despite it cost much to build system in initial and took longer time to transfer from the original proc
For the past few years, offline retailers have started to develop warehousing and logistics management further by information technology. Despite it cost much to build system in initial and took longer time to transfer from the original proc
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/cf4nub
Autor:
Ming-Hsuan Hsieh, Chin-Ming Fu, Tsung-Che Lu, Chih-Hsien Chang, Kenny Hsieh, Tien-Chien Huang
Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an
Autor:
Ching-Fang Chen, Saman M. I. Adham, Chin-Ming Fu, Wen-Hung Huang, Chih-Hsien Chang, Tien-Chien Huang, Mao-Hsuan Chou, Tze-Chiang Huang, Ying-Yu Hsu, Chien-Chun Tsai, William Wu Shen, Min-Jer Wang, Mu-Shan Lin, Ashok B. Mehta, Shu-Chun Yang
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1063-1074
A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ
Autor:
Chin-Hua Wen, Chiang Pu, Fu-Lung Hsueh, Chung-Wing Wong, Chih-Hsien Chang, Chin-Ming Fu, Wan-Te Chen, Yung-Chow Peng, Mu-Shan Lin, Li Yueh Wang, Chien-Chun Tsai, Tsung-Hsin Yu, Wei Chih Chen, Shu-Chun Yang, Wen-Hung Huang, Chi-Chang Lu, Jinn-Yeh Chien
Publikováno v:
CICC
This paper presents a 2.5–8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear equalizer (LEQ) and decision feedback equalizer (DFE) are used to eliminate ISI effect, compens
Autor:
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
Publikováno v:
2010 IEEE Custom Integrated Circuits Conference (CICC); 2010, p1-4, 4p