Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Chin Lee Kuan"'
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
Decoupling capacitors are required for power integrity performance. The use of package landside capacitors (LSCs) and/or board backside decoupling imposes significant design constraints on achievable system height. Low realizable capacitance due to l
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
Package design rules are traditionally determined by signal integrity reasons. However, these determine the total package inductance and the number of capacitors that can be installed, in turn determining the highest frequency impedance peak in the p
Publikováno v:
2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
High current voltage regulators for microelectronic loads like microprocessors and field programmable gate arrays have stringent overshoot requirements due to reliability and performance implications. Toward this end this paper presents two novel ind
Publikováno v:
2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
Merger of multiple loads on single voltage rail results in increase in self and coupling noise due to close proximity of load spatial distribution and limited package resources for individual isolation inductor. This paper presents a new filtering te
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
With modern low power circuits needing supply voltages around 0.6 [V], there is a growing need for accurately accounting for DC variations. To accentuate the problem proliferation of power supplies for extended battery life has forced tightly co-loca
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
Placement of discrete capacitors per unit area is restricted by solder resist opening (SRO) spacing rule. In addition to processor die size and bump pitch reduction over generations, number of voltage rail increase due to power management requirement
Publikováno v:
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper presents design considerations for grouping multiple loads to a common power plane. Power management & VR low load efficiency are covered briefly. The main focus is power integrity aspects to address differing load excitations, noise sensi
Publikováno v:
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper presents analysis & methodology for impedance design of distributed voltage domains supplied from high frequency voltage regulators (VRs). The approach addresses entire system including the combination of routing parasitics, decoupling cap
Publikováno v:
2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference.
Gated power delivery network (PDN) system design requires careful decoupling capacitor allocation between ungated and gated loads. This paper illustrates the pros and cons of ungated and gated capacitors to system performance based on impedance and l
Publikováno v:
2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference.
This paper analyses use of solid metal fill between BGA balls or LGA pins of packages, and between die bumps. The basic principle is to benefit from higher metal-density per unit volume of the substrate in the current path to deliver enhanced electri