Zobrazeno 1 - 10
of 270
pro vyhledávání: '"Chih-hang Tung"'
Publikováno v:
Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces. :69-93
Publikováno v:
Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces. :95-124
Autor:
Lombardo, Salvatore, Stathis, James H., Linder, Barry P., Kin Leong Pey, Palumbo, Felix, Chih Hang Tung
Publikováno v:
Journal of Applied Physics; 12/15/2005, Vol. 98 Issue 12, p121301, 36p, 1 Black and White Photograph, 12 Diagrams, 44 Graphs
Publikováno v:
IEEE Electron Device Letters. 29:1302-1305
The size dependence of the dielectric constants and optical absorption for silicon nanostructured films are investigated using density-functional theory. A critical thickness of 4.3 nm is observed for Si (100)-oriented thin films. Within this critica
Autor:
C. K. Cheng, Chee C. Wong, X. M. Li, Chih Hang Tung, King-Ning Tu, Y. K. Tan, Xingwang Zhang, Zhong Chen, Subodh Mhaisalkar
Publikováno v:
Journal of Nanoscience and Nanotechnology. 8:3999-4002
Copper films with high density of twin boundaries are known for high mechanical strength with little tradeoff in electrical conductivity. To achieve such a high density, twin lamellae and spacing will be on the nanoscale. In the current study, 10 mic
Publikováno v:
IEEE Electron Device Letters. 29:553-556
In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane treatment), alternative gold-free palladium-germanium (PdGe) source and drain (S/D) ohmic contacts,
Autor:
Keat-Mun Hoe, Chih-Hang Tung, D. Weeks, Michael Bauer, N. Balasubramanian, Yee-Chia Yeo, J. Spear, Kah-Wee Ang, Hoong-Shing Wong, Lap Chan, Ganesh S. Samudra, S.G. Thomas
Publikováno v:
IEEE Electron Device Letters. 29:460-463
We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions
Publikováno v:
Japanese Journal of Applied Physics. 47:2551-2555
We report a novel strained Si0.75Ge0.25 channel p-type field effect transistor (p-FET) that employs a silicon strain-transfer-layer (STL) buried beneath the channel. At the vertical heterojunction, the compliant silicon strain-transfer-layer, improve
Autor:
Chih-Hang Tung, Keat-Mun Hoe, Yee-Chia Yeo, N. Balasubramanian, Tsung-Yang Liow, Ming Zhu, Kian-Ming Tan, Ganesh S. Samudra, Rinus T. P. Lee
Publikováno v:
Japanese Journal of Applied Physics. 47:2589-2592
Strained p-channel tri-gate fin-type field-effect transistor (FinFET) with extended-Pi (eΠ) shaped SiGe source/drain (S/D) is demonstrated with enhanced drive current performance of 33% at a fixed drain induced barrier lowering (DIBL) over FinFET wi
Autor:
Jianqiang Lin, Kah-Wee Ang, Yee-Chia Yeo, Ganesh S. Samudra, N. Balasubramanian, Chih-Hang Tung
Publikováno v:
IEEE Transactions on Electron Devices. 55:850-857
A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D st