Zobrazeno 1 - 10
of 46
pro vyhledávání: '"Chih-Wei Yao"'
Publikováno v:
Materials, Vol 11, Iss 12, p 2559 (2018)
Localized impurities doped in the semiconductor substrate of nanostructure devices play an essential role in understanding and resolving transport and variability issues in device characteristics. Modeling discrete impurities under the framework of d
Externí odkaz:
https://doaj.org/article/41c2225eabeb49beb1c13f23fe7d2e53
Publikováno v:
European Respiratory Review, Vol 22, Iss 130, Pp 587-588 (2013)
Externí odkaz:
https://doaj.org/article/ae3474ebc7034bbe812e806c298c2dcc
Autor:
Chih-Wei Yao, 姚志偉
95
In order to replace nonylphenol polyoxyethylene ether and Bisphenol polyoxyethylene ether, a series of water soluble nonionic surfactants have been synthesized by reacting polyoxyethylene stearyl ether、polyoxyethylene glyceryl ether、polyo
In order to replace nonylphenol polyoxyethylene ether and Bisphenol polyoxyethylene ether, a series of water soluble nonionic surfactants have been synthesized by reacting polyoxyethylene stearyl ether、polyoxyethylene glyceryl ether、polyo
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/ac4vca
Autor:
Chih-Wei Yao, Wanghua Wu, Lei Chen, Chengkai Guo, Sang Won Son, Zhanjun Bai, Pak-Kim Lau, Thomas Byunghak Cho, Pei-Yuan Chiang
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:3756-3767
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-N phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-N mode, a phase detector r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6cfaad37a75c23d7bbfd464666c36bc
https://doi.org/10.1109/jssc.2021.3111134
https://doi.org/10.1109/jssc.2021.3111134
Autor:
Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee
Publikováno v:
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27380a86b87cd77965a041837f4c3240
https://doi.org/10.1109/esscirc55480.2022.9911419
https://doi.org/10.1109/esscirc55480.2022.9911419
Autor:
Ashutosh Verma, Venu Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang Ivan Lu, Sang Won Son, Thomas B. Cho
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6a22a92de88e7afc082256d5ba7787f
https://doi.org/10.1109/isscc42614.2022.9731664
https://doi.org/10.1109/isscc42614.2022.9731664
Autor:
Seungchan Heo, Ji-Soo Chang, Sanghoon Kang, Hyung-sun Lim, Sang-Wook Han, Jongwoo Lee, Il-Yong Jong, Ki Yong Son, Chih-Wei Yao, Joon-hee Lee, Ronghua Ni, Daechul Jeong, Thomas Byunghak Cho, Jaehyuk Jang, Yongrong Zuo, Jeong-Yeol Bae, Sang-Hyun Baek, Lee Jae-Hoon, Byoungjoong Kang, Seunghyun Oh, Inyup Kang
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:3541-3552
The world’s first single-chip RF transceiver to support 5G sub-6-GHz new radio (NR) and long-term evolution (LTE) E-UTRA New Radio-Dual Connectivity (EN-DC) in 14-nm FinFET CMOS technology is presented. The single-chip transceiver integrates identi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9087d36b11243c119d8c46d575670441
https://doi.org/10.1109/jssc.2019.2938132
https://doi.org/10.1109/jssc.2019.2938132
Autor:
Yongping Han, Yongrong Zuo, Chih-Wei Yao, Ashutosh Verma, Pei-Yuan Chiang, Wanghua Wu, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho, Kunal Godbole, Ronghua Ni
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:1254-1265
An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6cadde0fbcc9502dc1b149e80cb00f45
https://doi.org/10.1109/jssc.2019.2899726
https://doi.org/10.1109/jssc.2019.2899726
Autor:
Chih-Wei Yao, Sang Won Son, Lei Chen, Thomas Byunghak Cho, Chengkai Guo, Wanghua Wu, Pei-Yuan Chiang, Pak-Kim Lau
Publikováno v:
ISSCC
A local oscillator (LO) for 5G new radio requires sub-100fs rms jitter to support 64-OAM and $2\times2$ MIMO under non-ideal channel conditions [1]. Although fractional-N phase-locked loops (PLLs) employing digital-to-time converters (DTCs) and sampl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1e55f8afb2ca190c3a6dc99308f76fd
https://doi.org/10.1109/isscc42613.2021.9365850
https://doi.org/10.1109/isscc42613.2021.9365850
Autor:
Daehyeon Kwon, Chih-Wei Yao, Wanghua Wu, Sang-Wook Han, Chung Lau, Chul-Ho Kim, Kunal Godbole, Nam-Seog Kim, Ikkyun Jo, Sang Won Son, Ronghua Ni, Thomas Byunghak Cho, Sangsoo Ko, Shinwoong Kim, Yongrong Zuo, Joon-hee Lee, Juyoung Han
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:3446-3457
A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a09274874ee41c1022d7d9839e7c8462
https://doi.org/10.1109/jssc.2017.2742518
https://doi.org/10.1109/jssc.2017.2742518