Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Chien-wei Chien"'
Autor:
Chien-Wei Chien, 錢建維
103
With the evolution of the times, the pursuit of semiconductor products in addition to the reliability of the process, but often consider is that profit and cost, which ignoring the cost of failure (Enterprise’s sales, image and opportuniti
With the evolution of the times, the pursuit of semiconductor products in addition to the reliability of the process, but often consider is that profit and cost, which ignoring the cost of failure (Enterprise’s sales, image and opportuniti
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/mnmk4e
Autor:
Chien-Wei Chien, 簡建瑋
101
The purpose of this study was aimed to discover the relationship among surfers’ involvement, motivation, flow experience and behavior intention. In addition, the research also focused on whether or not involvement and motivation affected b
The purpose of this study was aimed to discover the relationship among surfers’ involvement, motivation, flow experience and behavior intention. In addition, the research also focused on whether or not involvement and motivation affected b
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/79148711292402166479
Autor:
Chien-Wei Chien, 簡健威
100
Many of the finance holding corporation has invested into insurance industry due to the highly competitive capital financial market. Nonetheless, these companies provided the similar services for the public that is hardly to interpret the di
Many of the finance holding corporation has invested into insurance industry due to the highly competitive capital financial market. Nonetheless, these companies provided the similar services for the public that is hardly to interpret the di
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/43079630968852398562
Publikováno v:
Microelectronics Reliability. 50:489-497
This study aims at developing an advanced clamped through-silicon via (C-TSV) interconnection technology for three-dimensional (3D) chip-to-chip or chip-to-wafer packaging. The special features of the C-TSV technology include (1) the proposal of meta
Publikováno v:
2008 58th Electronic Components and Technology Conference.
Immersion solder bumping, a mask-less and low cost processing, brings feasibility to the ultra-fine pitch chip-to- chip interconnection; however, how to make the uniform micro-bump is still a great challenge. In this paper, the uniform micro-bumps wi
Autor:
Jin-Ye Jaung, Chien-Wei Chien, Hsien-Chie Cheng, Yuan-Chang Lee, Li-Cheng Shen, Wei-Chung Lo, Chia-Te Lin, Chao-Kai Hsu, Yin-Po Hung
Publikováno v:
2008 58th Electronic Components and Technology Conference.
To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this pape
Autor:
Chin-Yao Chang, Li-Cheng Shen, Cheng-Ta Ko, Fang-Jun Leu, Chien-Wei Chien, Tsung-Fu Yang, Ying-Ching Shih, Yuan-Chang Lee, Tao-Chih Chang, Ching-Kuan Lee, Chao-Kai Shu
Publikováno v:
2007 Proceedings 57th Electronic Components and Technology Conference.
In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 m
Autor:
Tsung-Fu Yang, Chao-Kai Shu, Fang-Jun Leu, Tao-Chih Chang, Chin-Yao Chang, Chien-Wei Chien, Ying-Ching Shih, Cheng-Ta Ko, Li-Cheng Shen, Yuan-Chang Lee, Ching-Kuan Lee
Publikováno v:
2007 International Microsystems, Packaging, Assembly and Circuits Technology.
Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by diele
Autor:
Li-Cheng Shen, Chien-Wei Chien, Tao-Chih Chang, Tsung-Fu Yang, Wen-Chih Chen, Yin-Po Hung, Cheng-Ta Ko, Yuan-Chang Lee, Fang-Jun Leu, Ying-Ching Shih, Ingrid Wei, Carl Lei
Publikováno v:
2007 Proceedings 57th Electronic Components and Technology Conference.
By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type