Zobrazeno 1 - 10
of 72
pro vyhledávání: '"Chien-Hua HSU"'
Autor:
Pin-Ling CHANG, Chien-Hua HSU
Publikováno v:
transLogos: Translation Studies Journal, Vol 5, Iss 2, Pp 60-83 (2022)
In 2016, Google upgraded its translation system Google Translate (GT) from statistical-based machine translation (SMT) to neural-based machine translation (NMT), the latest machine translation (MT) technology so far, resulting in faster translation s
Externí odkaz:
https://doaj.org/article/14715124b7f449a9b9059aefe5ee52af
Autor:
Yu-De Lin, Pang-Shiu Chen, Heng-Yuan Lee, Yu-Sheng Chen, Sk. Ziaur Rahaman, Kan-Hsueh Tsai, Chien-Hua Hsu, Wei-Su Chen, Pei-Hua Wang, Ya-Chin King, Chrong Jung Lin
Publikováno v:
Nanoscale Research Letters, Vol 12, Iss 1, Pp 1-6 (2017)
Abstract A retention behavior model for self-rectifying TaO/HfO x - and TaO/AlO x -based resistive random-access memory (RRAM) is proposed. Trapping-type RRAM can have a high resistance state (HRS) and a low resistance state (LRS); the degradation in
Externí odkaz:
https://doaj.org/article/3d97a3c18f384278bd773d0cc0904cb6
Publikováno v:
ACS Applied Bio Materials. 5:3778-3787
Sulfonated copolyanilines (SPANs), SPAN-40 and SPAN-75, were prepared and applied in this tissue engineering study. SPAN scaffolds (SPANs) and control group polyaniline (PANI) were synthesized by performing oxidative polymerization. To further resear
Autor:
Hsin-Yun Yang, Shyh-Shyuan Sheu, Fu Yi-Keng, Li-Heng Lee, Yuh-Renn Wu, Po-Chun Yeh, Po-Tsung Tu, Pei-Jer Tzeng, Hsueh-Hsing Liu, Chien-Hua Hsu, Wei-Chung Lo, Chih-I Wu
Publikováno v:
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
In this work, we successfully fabricated AlGaN/GaN HEMT on 8-inch GaN-on-Si wafer utilizing CMOS BEOL compatible process, and demonstrate an AlGaN/GaN HEMT with L g = 250nm reaching f t /f max = 50/44 GHz. By semi-automatic RF measurements mapping in
Autor:
Wei-Chung Lo, Yu-Hao Chen, Shyh-Shyuan Sheu, Pei-Jer Tzeng, Tuo-Hung Hou, Hsin-Hui Huang, Yueh-Hua Chu, Chih-I Wu, Chien-Hua Hsu
Publikováno v:
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Ferroelectric tunnel junction (FTJ) with ultrathin 3 nm-thick Hf 0.5 Zr 0.5 O 2 (HZO) is investigated. The high current density up to 100 A/cm2 is at least 10 times higher than that in previously reported HZO FTJs. It is suitable for future nanoscale
Autor:
Rui-Da Chen, Yui Whei Chen-Yang, Chien-Hua Hsu, Ting-Yu Huang, Yuan-Xian Liu, Jui-Ming Yeh, Ting-Yu Chin
Publikováno v:
ACS biomaterials scienceengineering. 3(8)
In this paper, a biomolding technique was first used to fabricate a scaffold of hierarchical topography with biomimetic morphology for tissue engineering. First, poly(ortho-methoxyaniline) (POMA) was synthesized by conventional oxidative polymerizati
Autor:
Yu-De Lin, Kan-Hsueh Tsai, S. Z. Rahaman, Pei-Hua Wang, Yu-Sheng Chen, Heng-Yuan Lee, Ming-Jinn Tsai, Chien-Hua Hsu, Wei-Su Chen, Pang-Shiu Chen
Publikováno v:
Langmuir. 33:4654-4665
Ti/HfOx-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the
Autor:
Shyh-Shyuan Sheu, Heng-Yuan Lee, Yueh-Hua Chu, Wei-Chung Lo, Tuo-Hung Hou, Ming-Hung Wu, Chien-Hua Hsu, Tzu-Yun Wu, Hsin-Hui Huang
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/ capacitive/tunneling currents simultaneously is proposed. This model explains both
Autor:
Chien-Ting Wu, Yueh-Hua Chu, Min-Ci Wu, Tian-Sheuan Chang, Hsin-Hui Huang, Chih-Cheng Chang, Shyh-Shyuan Sheu, Wen-Wei Wu, Tzu-Yun Wu, Heng-Yuan Lee, Chien-Hua Hsu, Wei-Chung Lo, Ming-Hung Wu, Tuo-Hung Hou
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
This paper presents a unique opportunity of HZO ferroelectric tunnel junction (FTJ) for in-memory computing. The device operates at an extremely low sub-nA current while simultaneously achieving 50-ns fast switching, > 107 cycling endurance, > 10-yr
Autor:
Meng-Fan Chang, Kung-Tang Chang, Hai Li, Yi Chen, Qing Yang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Mon-Shu Ho, Bonan Yan, Wei-Hao Chen, Chien-Hua Hsu, Jian-Wei Su, Qing Wu
Publikováno v:
2019 Symposium on VLSI Technology.
This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller