Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Chien-Chou Wang"'
Autor:
Chien-chou Wang, 王建洲
96
Verifying that a hardware module connected to a bus follows the bus protocol correctly is a necessity in a bus-based System-on-Chip (SoC) development. Traditional simulation-based bus protocol monitors can check whether bus signals obey bus p
Verifying that a hardware module connected to a bus follows the bus protocol correctly is a necessity in a bus-based System-on-Chip (SoC) development. Traditional simulation-based bus protocol monitors can check whether bus signals obey bus p
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/38hj8h
Publikováno v:
IEICE Transactions on Information and Systems. :2100-2108
Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4f76fc860249eb3b1779721e94bb68b
https://doi.org/10.1587/transinf.e93.d.2100
https://doi.org/10.1587/transinf.e93.d.2100
Publikováno v:
ISCAS
Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to-market, thus how to verify IP functionality on bus protocol is a challenge. Traditional simulation-based bus protocol monitors can check
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a643aa596a7a2782a4a19a0b646405bc
https://doi.org/10.1109/iscas.2008.4541571
https://doi.org/10.1109/iscas.2008.4541571
Autor:
Chung-Nan Lee, Sheng-Yu Chiu, Tsung-Yu Ho, Ruei-Ting Gu, Ming-Chao Chiang, Chien-Chou Wang, Wen-Chi Shiue, Da-Jing Zhang-Jian, Tzu-Ching Tien, Jin-Hua Hong, Chung-Hua Tsai, Ing-Jer Huang, Shen-Fu Hsiao, Yun-Nan Chang, Wei-Sheng Huang
Publikováno v:
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55061541e559281e19b4ac01024d1537
https://doi.org/10.1109/vdat.2008.4542412
https://doi.org/10.1109/vdat.2008.4542412
Autor:
Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang
Publikováno v:
2008 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT); 2008, p59-62, 4p
Autor:
Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
Publikováno v:
2009 Asia & South Pacific Design Automation Conference; 2009, p131-132, 2p