Zobrazeno 1 - 4
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pro vyhledávání: '"Chieh-Yuan Chao"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16:58-77
The high cost of capital equipment for production testing coupled with the time that an analog circuit spends on a tester has made it imperative to minimize average chip testing time during production. Testing time can be reduced by decreasing the nu
Autor:
Chieh-Yuan Chao, L. Milor
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 8:239-251
Circuit designers need to be able to predict variations in circuit performance as a function of variations in process parameters. Often the relation between process parameters and circuit performances is highly nonlinear, and the process is described
Publikováno v:
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.
Attempts to reduce production testing time by presenting a fault-driven methodology to handle LSI analog circuits. A fault-driven methodology has to be able to detect both parametric and catastrophic faults. For statistical performance simulation to
Autor:
L. Milor, Chieh-Yuan Chao
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
Circuit designers need to be able to predict variations in circuit performance as a function of variations in process parameters. Often the relation between process parameters and circuit performances is highly nonlinear, and the process is described