Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Chidi Chidambaram"'
Autor:
S.C. Song, Giri Nallapati, Irfan Khan, Nader Nikfar, Bohan Yan, Miguel Miranda, Bruce Lim, Mali Nagarajan, Joon-Young Park, Vaishnav Srinivas, Reza Langari, Bharani Chava, Venu Sanaka, Venu Boynapalli, Paras Gupta, Shree Pandey, Biancun Xie, Peijie Feng, Jihong Choi, Titash Rakshit, Ravi Shenoy, Mahadev Nemani, Colin Verrilli, John Zhu, Jun Chen, Mark Nakamoto, Lily Zhao, Yangyang Sun, Francois Atallah, Jonghae Kim, Rashid Attar, Chidi Chidambaram
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Autor:
Leo Kim, Yuri Y. Masuoka, Paul Ivan Penzes, Giri Nallapati, Ying Chen, Venu Boynapalli, S. C. Song, Jason Cheng, Lixin Ge, Sung-Won Kim, Chidi Chidambaram, Rajagopal Narayanan, Xiao-Yong Wang, Jihong Choi, Ukjin Roh, Jerry Bao, Hyejun Jin, Byungmoo Song, Deepak Sharma, Gary Chen, Ming Cai, Zhimin Song, Jie Deng, Jin-Kyu Lee, Vicki Lin, Hao Wang, Kwon Lee, Suh Youseok
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We report on Qualcomm® Snapdragon™ 765 mobile Platform and world's first integrated 5G platform supporting both mmWave and sub-6 using industry-leading 7nm EUV FinFET technology. Snapdragon 765 unites 5G and AI to power select premium-tier experie
Autor:
Xi-Wei Lin, Nicolas Breil, Michael Chudzik, Chidi Chidambaram, S. C. Song, Munkang Choi, Victor Moroz, Benjamin Colombeau, Qiang Lu, Giri Nallapati, Jerry Bao, Peijie Feng, John Jianhong Zhu
Publikováno v:
IEEE Electron Device Letters. 38:1657-1660
This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) archi
Autor:
X-W. Lin, Victor Moroz, Jacky Huang, B. Cheng, Chidi Chidambaram, Munkang Choi, D. Sherlekar, S. C. Song, P. Asenov, Sanjay Natarajan, Matthias Bauer, Benjamin Colombeau
Publikováno v:
2019 Symposium on VLSI Technology.
We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm n
Autor:
Po-Wen Chan, Jeff Xu, Jeffrey Smith, Jerry Bao, S. C. Song, Keagan Chen, Da Yang, Naoto Horiguchi, Suman Datta, David Kohen, Mustafa Badaroglu, Hans Mertens, Peijie Feng, John Jianhong Zhu, Geert Eneman, Romain Ritzenthaler, P. R. Chidi Chidambaram
Publikováno v:
ESSDERC
We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for bett
Autor:
Jeffrey Smith, Jeff Xu, Suman Datta, Kai Ni, Mustafa Badaroglu, P. R. Chidi Chidambaram, Ram Krishna Ghosh
Publikováno v:
ESSDERC
This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs.
Autor:
Chidi Chidambaram, Iuliana Radu, T. Tsunomura, Carlos Mazure, D. McCann, Huiming Bu, Jason C. S. Woo, Dan Mocuta
Publikováno v:
2017 Symposium on VLSI Technology.
The FINFET has become widely used for nodes below 16nm. Its introduction in the manufacturing world has extended scalability of transistor dimensions. Beyond 5nm it is uncertain if the benefits of a FINFET structure will be maintained or lost. Altern
Autor:
Ping Liu, Sung-Gun Kang, Jackie Yang, S. C. Song, Xiao-Yong Wang, Yanxiang Liu, Jedon Kim, Yandong Gao, Lixin Ge, Suh Youseok, Sam Yang, Jie Deng, Sung-Won Kim, Xiangdong Chen, Peijie Feng, Ken Rim, John Jianhong Zhu, Ming Cai, Chul-Yong Park, Da Yang, Jun Yuan, Hao Wang, Jihong Choi, Esin Terzioglu, P. R. Chidi Chidambaram, Jerry Bao, Paul Ivan Penzes
Publikováno v:
2017 Symposium on VLSI Technology.
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The
Autor:
Jason C. S. Woo, Joseph Wang, P. R. Chidi Chidambaram, Seung Chul Song, Frank Yang, Po-Yen Chien, Geoffrey Yeap
Publikováno v:
Microelectronics Reliability. 54:1090-1095
Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage ( V TH ) variability has emerged as a major challenge for circuit a
Autor:
Venu Boynapalli, Michael Han, ChangHo Jung, Sei Seung Yoon, Geoffrey Yeap, Giri Nallapati, Joseph Wang, Mohamed Hassan Abu-Rahma, Sam Yang, Chidi Chidambaram, Aaron Thean, Ritu Chaba, Esin Terzioglu, Mehdi Hamidi Sani
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are describe